From patchwork Thu Oct 29 23:20:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Van Brunt X-Patchwork-Id: 7522121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AD1739F750 for ; Thu, 29 Oct 2015 23:24:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D4A9620883 for ; Thu, 29 Oct 2015 23:24:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0122F20879 for ; Thu, 29 Oct 2015 23:24:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZrwWa-0005oe-5m; Thu, 29 Oct 2015 23:22:28 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZrwTx-0002JA-GD for linux-arm-kernel@lists.infradead.org; Thu, 29 Oct 2015 23:19:47 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 29 Oct 2015 16:19:23 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 29 Oct 2015 16:17:37 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 29 Oct 2015 16:17:37 -0700 Received: from avanbrunt-dt.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Thu, 29 Oct 2015 16:19:25 -0700 From: Alex Van Brunt To: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Will Deacon , Sudeep Holla , Catalin Marinas Subject: [PATCH v2 4/4] arm64: document the cache policy behavior Date: Thu, 29 Oct 2015 16:20:42 -0700 Message-ID: <1446160842-25787-4-git-send-email-avanbrunt@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1446160842-25787-1-git-send-email-avanbrunt@nvidia.com> References: <1446160842-25787-1-git-send-email-avanbrunt@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151029_161945_743097_CAD8F7EA X-CRM114-Status: GOOD ( 12.04 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Van Brunt , stable@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a comment that clairfies how the kernel should behave given the cache policy reported by the CPU. Signed-off-by: Alex Van Brunt Cc: --- arch/arm64/kernel/cpuinfo.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index ae04ac1..bf7e5e2 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -49,6 +49,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) unsigned int cpu = smp_processor_id(); u32 l1ip = CTR_L1IP(info->reg_ctr); + /* + * The ARM architecture defines PIPT, VIPT and AIVIVT in terms of the + * the observable behavior not how the CPU implements the policy. + * Specifically, the policies differentiate the correct way to + * invalidate the cache. The definitions say that the only + * architecturally guaranteed way to invalidate a VIPT or AIVIVT + * instruction cache is to invalidate the entire instruction cache. + */ if (l1ip != ICACHE_POLICY_PIPT) set_bit(ICACHEF_ALIASING, &__icache_flags); if (l1ip == ICACHE_POLICY_AIVIVT)