From patchwork Fri Nov 6 00:37:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 7565071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9B6149F4F5 for ; Fri, 6 Nov 2015 00:39:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A6535207AA for ; Fri, 6 Nov 2015 00:39:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 740B520801 for ; Fri, 6 Nov 2015 00:39:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZuV2k-0004uY-Cd; Fri, 06 Nov 2015 00:38:14 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZuV2h-0004q3-Mz for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2015 00:38:12 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 055F0140087; Fri, 6 Nov 2015 00:37:51 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id E4FD814011E; Fri, 6 Nov 2015 00:37:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from timur-ubuntu.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AD40B140087; Fri, 6 Nov 2015 00:37:48 +0000 (UTC) From: Timur Tabi To: linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew.Jackson@arm.com, andre.przywara@arm.com, jun.nie@linaro.or, peter@hurleysoftware.com, Linus Walleij , Greg Kroah-Hartman , jslaby@suse.com, rmk+kernel@arm.linux.org.uk Subject: [PATCH] tty: amba-pl011: add options to earlycon for 32-bit reg access Date: Thu, 5 Nov 2015 18:37:47 -0600 Message-Id: <1446770267-26749-1-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151105_163811_852635_AED1F4B1 X-CRM114-Status: GOOD ( 16.37 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the "sbsa32" command-line option to earlycon to specify that the pl011 registers should be accessed with 32-bit accessors only. This is SBSA platforms Similarly, also add the "zte" option for the ZTE UART. It's functionally similar to the standard PL011, but some registers are at different offsets. Normal console uses the "access_32b" field of the vendor data structure to determine whether the registers needs 32-bit accessors. Early console is used before the vendor data is available, so we need a different mechanism to choose the accessor. Example: earlycon=pl011,0x3ced1000,sbsa32 Signed-off-by: Timur Tabi --- This patch applies on top of Russell's 12-part amba-pl011.c patchset. drivers/tty/serial/amba-pl011.c | 46 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 373b152..58eda89 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2301,10 +2301,10 @@ static struct console amba_console = { static void pl011_putc(struct uart_port *port, int c) { - while (readl(port->membase + REG_FR) & UART01x_FR_TXFF) + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) ; - writeb(c, port->membase + REG_DR); - while (readl(port->membase + REG_FR) & UART01x_FR_BUSY) + writeb(c, port->membase + UART01x_DR); + while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) ; } @@ -2315,13 +2315,51 @@ static void pl011_early_write(struct console *con, const char *s, unsigned n) uart_console_write(&dev->port, s, n, pl011_putc); } +static void pl011_putc_sbsa32(struct uart_port *port, int c) +{ + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) + cpu_relax(); + writel(c, port->membase + UART01x_DR); + while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) + cpu_relax(); +} + +static void pl011_early_write_sbsa32(struct console *con, const char *s, unsigned n) +{ + struct earlycon_device *dev = con->data; + + uart_console_write(&dev->port, s, n, pl011_putc_sbsa32); +} + +static void pl011_putc_zte(struct uart_port *port, int c) +{ + while (readl(port->membase + ZX_UART011_FR) & UART01x_FR_TXFF) + cpu_relax(); + writel(c, port->membase + ZX_UART011_DR); + while (readl(port->membase + ZX_UART011_FR) & UART01x_FR_BUSY) + cpu_relax(); +} + +static void pl011_early_write_zte(struct console *con, const char *s, unsigned n) +{ + struct earlycon_device *dev = con->data; + + uart_console_write(&dev->port, s, n, pl011_putc_zte); +} + static int __init pl011_early_console_setup(struct earlycon_device *device, const char *opt) { if (!device->port.membase) return -ENODEV; - device->con->write = pl011_early_write; + if (strcmp(device->options, "sbsa32") == 0) + device->con->write = pl011_early_write_sbsa32; + else if (strcmp(device->options, "zte") == 0) + device->con->write = pl011_early_write_zte; + else + device->con->write = pl011_early_write; + return 0; } EARLYCON_DECLARE(pl011, pl011_early_console_setup);