From patchwork Wed Nov 11 05:48:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 7593801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D70909F392 for ; Wed, 11 Nov 2015 05:51:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E18332055A for ; Wed, 11 Nov 2015 05:51:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F05BE2051F for ; Wed, 11 Nov 2015 05:51:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZwOHC-0006Hn-S6; Wed, 11 Nov 2015 05:48:58 +0000 Received: from mail-pa0-f45.google.com ([209.85.220.45]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZwOH7-0006Ef-Df; Wed, 11 Nov 2015 05:48:55 +0000 Received: by padhx2 with SMTP id hx2so21174251pad.1; Tue, 10 Nov 2015 21:48:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id; bh=kzKzwALzxG7gTACnSbs7hohqqilHurK49ANLhGf7NTw=; b=bf3dd++r7Kg/aJxOq10TI9zFeUh31Lwv2ylijXZLa7d9aQD1F9blxcvECp89qz2sXs 2SOUKVBoeRXtqTl5vw2LzIlem9Eon3b0aA7ji2d233/FdgkGzrQZFrwc5m4C92LNCn1x jHDgO8tAClecaexBbkRGjqxt21jDKT3h4GdBOKP9fPJiIYLprKzmGLZZvCQH1uhbTRH7 EFRApFQxWx5mxXqQg0pwL47cN8AHRzwp0dtwowZ2SCL3QYAu6TJgnKwmgaWwZImmwdvi qTm0w/9ADX8YgW+t/w2l49RVyIOA7l/pLJ90Kj9FQ6CvGFs/zCLhwsH8K9M0GWXGb0w4 n6Ig== X-Received: by 10.68.92.194 with SMTP id co2mr11633251pbb.125.1447220911294; Tue, 10 Nov 2015 21:48:31 -0800 (PST) Received: from localhost.localdomain ([192.253.253.154]) by smtp.gmail.com with ESMTPSA id zi1sm7394057pbc.10.2015.11.10.21.48.22 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 Nov 2015 21:48:30 -0800 (PST) From: Chris Zhong To: dianders@chromium.org Subject: [PATCH v2] clk: rockchip: switch PLLs to slow mode before reboot for rk3288 Date: Wed, 11 Nov 2015 13:48:11 +0800 Message-Id: <1447220891-14900-1-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151110_214853_519896_C105322E X-CRM114-Status: GOOD ( 14.37 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We've been seeing some crashes at reboot test on rk3288-based systems, which boards have not reset pin connected to NPOR, they reboot by setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in a high frequency mode, some IPs might hang during soft reset. It appears that we can fix the problem by switching to slow mode before reboot, just like what we did before suspend. Signed-off-by: Chris Zhong Reviewed-by: Heiko Stuebner --- Changes in v2: replace restart_handlers with the shutdown callback of syscore drivers/clk/rockchip/clk-rk3288.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 9040878..5ce44af 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "clk.h" @@ -783,9 +784,9 @@ static const char *const rk3288_critical_clocks[] __initconst = { "pclk_pd_pmu", }; -#ifdef CONFIG_PM_SLEEP static void __iomem *rk3288_cru_base; +#ifdef CONFIG_PM_SLEEP /* Some CRU registers will be reset in maskrom when the system * wakes up from fastboot. * So save them before suspend, restore them after resume. @@ -839,34 +840,32 @@ static void rk3288_clk_resume(void) rk3288_cru_base + reg_id); } } +#endif -static struct syscore_ops rk3288_clk_syscore_ops = { - .suspend = rk3288_clk_suspend, - .resume = rk3288_clk_resume, -}; - -static void rk3288_clk_sleep_init(void __iomem *reg_base) +static void rk3288_clk_shutdown(void) { - rk3288_cru_base = reg_base; - register_syscore_ops(&rk3288_clk_syscore_ops); + writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); } -#else /* CONFIG_PM_SLEEP */ -static void rk3288_clk_sleep_init(void __iomem *reg_base) {} +static struct syscore_ops rk3288_clk_syscore_ops = { +#ifdef CONFIG_PM_SLEEP + .suspend = rk3288_clk_suspend, + .resume = rk3288_clk_resume, #endif + .shutdown = rk3288_clk_shutdown, +}; static void __init rk3288_clk_init(struct device_node *np) { - void __iomem *reg_base; struct clk *clk; - reg_base = of_iomap(np, 0); - if (!reg_base) { + rk3288_cru_base = of_iomap(np, 0); + if (!rk3288_cru_base) { pr_err("%s: could not map cru region\n", __func__); return; } - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); /* xin12m is created by an cru-internal divider */ clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); @@ -907,10 +906,13 @@ static void __init rk3288_clk_init(struct device_node *np) &rk3288_cpuclk_data, rk3288_cpuclk_rates, ARRAY_SIZE(rk3288_cpuclk_rates)); - rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0), + rockchip_register_softrst(np, 12, + rk3288_cru_base + RK3288_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_register_restart_notifier(RK3288_GLB_SRST_FST); - rk3288_clk_sleep_init(reg_base); + + register_syscore_ops(&rk3288_clk_syscore_ops); +; } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);