From patchwork Fri Nov 13 12:31:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 7611341 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 25A8A9F1C2 for ; Fri, 13 Nov 2015 12:37:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 514F720794 for ; Fri, 13 Nov 2015 12:37:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 719092077E for ; Fri, 13 Nov 2015 12:37:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZxDZl-00086T-0L; Fri, 13 Nov 2015 12:35:33 +0000 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZxDZi-00084d-Q6 for linux-arm-kernel@lists.infradead.org; Fri, 13 Nov 2015 12:35:31 +0000 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id tADCYcP0013540; Fri, 13 Nov 2015 04:35:03 -0800 Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 1y59qx10qp-2 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 13 Nov 2015 04:35:03 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Fri, 13 Nov 2015 04:35:01 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Fri, 13 Nov 2015 04:35:01 -0800 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id 8EFFD3F7040; Fri, 13 Nov 2015 04:35:00 -0800 (PST) From: Jisheng Zhang To: , , Subject: [PATCH v2] clocksource/drivers/dw_apb_timer: Use {readl|writel}_relaxed Date: Fri, 13 Nov 2015 20:31:23 +0800 Message-ID: <1447417883-7881-1-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.2 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-11-13_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1511130211 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151113_043530_984173_6C559C6C X-CRM114-Status: GOOD ( 10.79 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jisheng Zhang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The driver is safe to use the relaxed version. From another side, the relaxed io accessor macros are available on all architectures now, so we can use the relaxed versions to get a trivial overall system performance improvement and reduce the latency a bit on some architectures. Signed-off-by: Jisheng Zhang --- since v1: - correct the wrong sentence in commit msg about writel performance on CA9 with outer L2 cache. Thank Arnd for pointing out this in another thread drivers/clocksource/dw_apb_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c index c76c750..04282ee 100644 --- a/drivers/clocksource/dw_apb_timer.c +++ b/drivers/clocksource/dw_apb_timer.c @@ -51,13 +51,13 @@ clocksource_to_dw_apb_clocksource(struct clocksource *cs) static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs) { - return readl(timer->base + offs); + return readl_relaxed(timer->base + offs); } static void apbt_writel(struct dw_apb_timer *timer, unsigned long val, unsigned long offs) { - writel(val, timer->base + offs); + writel_relaxed(val, timer->base + offs); } static void apbt_disable_int(struct dw_apb_timer *timer)