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Tue, 17 Nov 2015 06:57:02 -0800 (PST) From: Carlo Caione To: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux@arm.linux.org.uk, linux-meson@googlegroups.com, drake@endlessm.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, pawel.moll@arm.com, arnd@arndb.de Subject: [PATCH 5/7] Documentation: bindings: Add SMP related documentation Date: Tue, 17 Nov 2015 15:56:40 +0100 Message-Id: <1447772202-12418-6-git-send-email-carlo@caione.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1447772202-12418-1-git-send-email-carlo@caione.org> References: <1447772202-12418-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151117_065720_983838_0A33B885 X-CRM114-Status: GOOD ( 17.42 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlo Caione MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione With this patch we add documentation for: * power-management-unit: the PMU is used to bring up the cores during SMP operations * sram: among other things the sram is used to store the first code executed by the core when it is powered up * cpu-enable-method: the CPU enable method used by Amlogic Meson8b SoCs Signed-off-by: Carlo Caione --- .../devicetree/bindings/arm/amlogic/pmu.txt | 16 +++++++ .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 +++++++++++++ .../arm/cpu-enable-method/amlogic,meson8b-smp | 53 ++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file mode 100644 index 0000000..7b9b2da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt @@ -0,0 +1,16 @@ +Amlogic power-management-unit: +------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : = "amlogic,meson8b-pmu"; +- reg : physical base address and the size of the registers window + +Example: + + pmu@c81000e4 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xc81000e0 0x18>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt new file mode 100644 index 0000000..455ca20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt @@ -0,0 +1,32 @@ +Amlogic SRAM for smp bringup: +------------------------------ + +Amlogic's smp-capable SoCs use part of the sram for the bringup of the cores. +Once the core gets powered up it executes the code that is residing at a +specific location. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Required sub-node properties: +- compatible : should be "amlogic,meson8b-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram: sram@d9000000 { + compatible = "mmio-sram"; + reg = <0xd9000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd9000000 0x20000>; + + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; + }; + + diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp new file mode 100644 index 0000000..95ee458b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp @@ -0,0 +1,53 @@ +========================================================= +Secondary CPU enable-method "amlogic,meson8b-smp" binding +========================================================= + +This document describes the "amlogic,meson8b-smp" method for enabling secondary +CPUs. To apply to all CPUs, a single "amlogic,meson8b-smp" enable method should +be defined in the "cpus" node. + +Enable method name: "amlogic,meson8b-smp" +Compatible machines: "amlogic,meson8b" +Compatible CPUs: "arm,cortex-a5" +Related properties: (none) + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "amlogic,meson8b-smp"; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x200>; + resets = <&clkc RST_CORE0>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x201>; + resets = <&clkc RST_CORE1>; + }; + + cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x202>; + resets = <&clkc RST_CORE2>; + }; + + cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x203>; + resets = <&clkc RST_CORE3>; + }; + }; +