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[207.114.172.147]) by smtp.gmail.com with ESMTPSA id er1sm12635730pbb.6.2015.11.19.14.07.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2015 14:07:23 -0800 (PST) From: Moritz Fischer To: atull@opensource.altera.com Subject: [PATCH v2] fpga: zynq-fpga: Enable pm_runtime (suspend, resume) Date: Thu, 19 Nov 2015 14:07:12 -0800 Message-Id: <1447970832-774-1-git-send-email-moritz.fischer@ettus.com> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151119_140745_119944_712AB60D X-CRM114-Status: GOOD ( 16.75 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Moritz Fischer , gregkh@linuxfoundation.org, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, soren.brinkmann@xilinx.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Replaced constant clock_{enable,disable} calls with pm_runtime hooks for suspend and resume to avoid constant clk_enable / clk_disable. Acked-by: Alan Tull Signed-off-by: Moritz Fischer --- Changes: v1: - Removed superfluous #ifdef CONFIG_PM as suggested by Michal - Changed commit message to include suspend / resume - Added Alan's Acked-by drivers/fpga/zynq-fpga.c | 76 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 17 deletions(-) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index c2fb412..3f5469d 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -184,8 +185,8 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, priv = mgr->priv; - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) return err; /* don't globally reset PL if we're doing partial reconfig */ @@ -271,12 +272,12 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, ctrl = zynq_fpga_read(priv, MCTRL_OFFSET); zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl)); - clk_disable(priv->clk); + pm_runtime_put(priv->dev); return 0; out_err: - clk_disable(priv->clk); + pm_runtime_put(priv->dev); return err; } @@ -301,9 +302,8 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, memcpy(kbuf, buf, count); - /* enable clock */ - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) goto out_free; zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK); @@ -335,7 +335,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, err = -EFAULT; } - clk_disable(priv->clk); + pm_runtime_put(priv->dev); out_free: dma_free_coherent(priv->dev, in_count, kbuf, dma_addr); @@ -349,8 +349,8 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) int err; u32 intr_status; - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) return err; err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, @@ -358,7 +358,7 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) INIT_POLL_DELAY, INIT_POLL_TIMEOUT); - clk_disable(priv->clk); + pm_runtime_put(priv->dev); if (err) return err; @@ -385,12 +385,12 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) priv = mgr->priv; - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) return FPGA_MGR_STATE_UNKNOWN; intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); - clk_disable(priv->clk); + pm_runtime_put(priv->dev); if (intr_status & IXR_PCFG_DONE_MASK) return FPGA_MGR_STATE_OPERATING; @@ -457,19 +457,26 @@ static int zynq_fpga_probe(struct platform_device *pdev) return err; } + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + /* unlock the device */ zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); - clk_disable(priv->clk); err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", &zynq_fpga_ops, priv); if (err) { dev_err(dev, "unable to register FPGA manager"); - clk_unprepare(priv->clk); + clk_disable_unprepare(priv->clk); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); return err; } + pm_runtime_put(&pdev->dev); + return 0; } @@ -483,11 +490,45 @@ static int zynq_fpga_remove(struct platform_device *pdev) fpga_mgr_unregister(&pdev->dev); - clk_unprepare(priv->clk); + pm_runtime_get_sync(&pdev->dev); + clk_disable_unprepare(priv->clk); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); return 0; } +static int __maybe_unused zynq_fpga_runtime_suspend(struct device *dev) +{ + struct zynq_fpga_priv *priv; + struct fpga_manager *mgr; + + mgr = dev_get_drvdata(dev); + priv = mgr->priv; + + clk_disable(priv->clk); + + return 0; +} + +static int __maybe_unused zynq_fpga_runtime_resume(struct device *dev) +{ + struct zynq_fpga_priv *priv; + struct fpga_manager *mgr; + + mgr = dev_get_drvdata(dev); + priv = mgr->priv; + + clk_enable(priv->clk); + + return 0; +} + +static const struct dev_pm_ops zynq_fpga_pm_ops = { + SET_RUNTIME_PM_OPS(zynq_fpga_runtime_suspend, + zynq_fpga_runtime_resume, NULL) +}; + #ifdef CONFIG_OF static const struct of_device_id zynq_fpga_of_match[] = { { .compatible = "xlnx,zynq-devcfg-1.0", }, @@ -503,6 +544,7 @@ static struct platform_driver zynq_fpga_driver = { .driver = { .name = "zynq_fpga_manager", .of_match_table = of_match_ptr(zynq_fpga_of_match), + .pm = &zynq_fpga_pm_ops, }, };