From patchwork Fri Nov 20 08:35:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 7665831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BA55BC05CC for ; Fri, 20 Nov 2015 08:38:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2BB0204A2 for ; Fri, 20 Nov 2015 08:38:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D8DE203F7 for ; Fri, 20 Nov 2015 08:38:16 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZzhAu-0005vS-Mk; Fri, 20 Nov 2015 08:36:08 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZzhAj-0005ot-G7 for linux-arm-kernel@lists.infradead.org; Fri, 20 Nov 2015 08:35:58 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 610BD1401B0; Fri, 20 Nov 2015 08:35:40 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 5174C1401B5; Fri, 20 Nov 2015 08:35:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CE21A1401B0; Fri, 20 Nov 2015 08:35:39 +0000 (UTC) From: Andy Gross To: linux-arm-msm@vger.kernel.org Subject: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Date: Fri, 20 Nov 2015 02:35:09 -0600 Message-Id: <1448008509-8913-5-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1448008509-8913-1-git-send-email-agross@codeaurora.org> References: <1448008509-8913-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151120_003557_568273_F7D11B9C X-CRM114-Status: GOOD ( 12.26 ) X-Spam-Score: -3.2 (---) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Greg KH , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Felipe Balbi , Kishon Vijay Abraham I , Andy Gross , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds documentation for the optional syscon-tcsr property in the Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to configure the TCSR USB phy mux register. Signed-off-by: Andy Gross Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt index ca164e7..dfa222d 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -8,6 +8,10 @@ Required properties: "core" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation +Optional properties: +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for + configuring the phy mux setting. + Optional clocks: "iface" System bus AXI clock. Not present on all platforms "sleep" Sleep clock, used when USB3 core goes into low @@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt Example device nodes: + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + hs_phy: phy@100f8800 { compatible = "qcom,dwc3-hs-usb-phy"; reg = <0x100f8800 0x30>; @@ -51,6 +60,8 @@ Example device nodes: ranges; + syscon-tcsr = <&tcsr 0xb0 0x1>; + status = "ok"; dwc3@10000000 {