| Message ID | 1448178839-3541-8-git-send-email-mw@semihalf.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sunday 22 November 2015 08:53:53 Marcin Wojtas wrote: > This commit enables finding appropriate mbus window and obtaining its > target id and attribute for given physical address in two separate > routines, both for IO and DRAM windows. This functionality > is needed for Armada XP/38x Network Controller's Buffer Manager and > PnC configuration. > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > [DRAM window information reference in LKv3.10] > Signed-off-by: Evan Wang <xswang@marvell.com> > It's too long ago to remember all the details, but I thought we had designed this so the configuration can just be done by describing it in DT. What am I missing? Arnd
Arnd, 2015-11-22 21:02 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: > On Sunday 22 November 2015 08:53:53 Marcin Wojtas wrote: >> This commit enables finding appropriate mbus window and obtaining its >> target id and attribute for given physical address in two separate >> routines, both for IO and DRAM windows. This functionality >> is needed for Armada XP/38x Network Controller's Buffer Manager and >> PnC configuration. >> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com> >> >> [DRAM window information reference in LKv3.10] >> Signed-off-by: Evan Wang <xswang@marvell.com> >> > > It's too long ago to remember all the details, but I thought we > had designed this so the configuration can just be done by > describing it in DT. What am I missing? > And those functions do not break this approach. They just enable finding and reading the settings of MBUS windows done during initial configuration. Please remember that mvebu-mbus driver fills the MBUS windows registers basing on DT, however it just configures access CPU - DRAM/perfipheral. In this particular case only physical adresses of buffers are known and we have to 'open windows' between BM <-> DRAM and NETA <-> BM internal memory. Hence instead of hardcoding size/target/attribute, we can take information stored in CPU DRAM/IO windows registers. Best regards, Marcin
On Sunday 22 November 2015 22:24:01 Marcin Wojtas wrote: > > 2015-11-22 21:02 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: > > On Sunday 22 November 2015 08:53:53 Marcin Wojtas wrote: > >> This commit enables finding appropriate mbus window and obtaining its > >> target id and attribute for given physical address in two separate > >> routines, both for IO and DRAM windows. This functionality > >> is needed for Armada XP/38x Network Controller's Buffer Manager and > >> PnC configuration. > >> > >> Signed-off-by: Marcin Wojtas <mw@semihalf.com> > >> > >> [DRAM window information reference in LKv3.10] > >> Signed-off-by: Evan Wang <xswang@marvell.com> > >> > > > > It's too long ago to remember all the details, but I thought we > > had designed this so the configuration can just be done by > > describing it in DT. What am I missing? > > > > And those functions do not break this approach. They just enable > finding and reading the settings of MBUS windows done during initial > configuration. Please remember that mvebu-mbus driver fills the MBUS > windows registers basing on DT, however it just configures access CPU > - DRAM/perfipheral. > > In this particular case only physical adresses of buffers are known > and we have to 'open windows' between BM <-> DRAM and NETA <-> BM > internal memory. Hence instead of hardcoding size/target/attribute, we > can take information stored in CPU DRAM/IO windows registers. > > Ok, got it. Thanks for the explanation. Arnd
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index c43c3d2..3d1c0c3 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c @@ -948,6 +948,57 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res) *res = mbus_state.pcie_io_aperture; } +int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) +{ + const struct mbus_dram_target_info *dram; + int i; + + /* Get dram info */ + dram = mv_mbus_dram_info(); + if (!dram) { + pr_err("missing DRAM information\n"); + return -ENODEV; + } + + /* Try to find matching DRAM window for phyaddr */ + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + if (cs->base <= phyaddr && phyaddr <= (cs->base + cs->size)) { + *target = dram->mbus_dram_target_id; + *attr = cs->mbus_attr; + return 0; + } + } + + pr_err("invalid dram address 0x%x\n", phyaddr); + return -EINVAL; +} +EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info); + +int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target, + u8 *attr) +{ + int win; + + for (win = 0; win < mbus_state.soc->num_wins; win++) { + u64 wbase; + int enabled; + + mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase, + size, target, attr, NULL); + + if (!enabled) + continue; + + if (wbase <= phyaddr && phyaddr <= wbase + *size) + return win; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info); + static __init int mvebu_mbus_debugfs_init(void) { struct mvebu_mbus_state *s = &mbus_state; diff --git a/include/linux/mbus.h b/include/linux/mbus.h index 1f7bc63..ea34a86 100644 --- a/include/linux/mbus.h +++ b/include/linux/mbus.h @@ -69,6 +69,9 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(vo int mvebu_mbus_save_cpu_target(u32 *store_addr); void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr); +int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target, + u8 *attr); int mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size,