From patchwork Wed Nov 25 05:24:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jassi Brar X-Patchwork-Id: 7695201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4B4C79F2E9 for ; Wed, 25 Nov 2015 05:28:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7AFCC208B5 for ; Wed, 25 Nov 2015 05:28:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A73CB208B1 for ; Wed, 25 Nov 2015 05:28:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a1SZX-00059B-Hk; Wed, 25 Nov 2015 05:24:51 +0000 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a1SZU-00058U-79 for linux-arm-kernel@lists.infradead.org; Wed, 25 Nov 2015 05:24:49 +0000 Received: by pacej9 with SMTP id ej9so45619140pac.2 for ; Tue, 24 Nov 2015 21:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=bIehCwe4L1gopO6gGqXTh6xPxGUyPMtOBUs5POqLzsw=; b=lsOQRPFnH5FaLP6nfOk0LItT6PEJhhasLeLoLiWyfncJMnCGJtrzCkq/DNCi6BOPmW Yg9gko1xNJIX5DWN7dE76VrMGzf7aF5bLDznis0HEOl2yot56gQYPZQHup15+k2pho8+ 1LfNIyJ1LduqBPHXUhmIrtEHkpRLeCJc32qFu5okALQcXNH2Awlydvstj62KDCwossAa KIfuN72uKB2Rzh9KK6lmvK2Ms+HqjPEYcoGHk6k0zyTrdBIDFFhaLSevE7YfZ96m6FoD bwtSye47rrtLUSCqD/fm9/OTbTvG+lL/fTA42qxoagWKRAqm8iTvfE11TJS5snYdeu4X xFxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bIehCwe4L1gopO6gGqXTh6xPxGUyPMtOBUs5POqLzsw=; b=SZ0H4z4iksA/4m/WVDtKHDbq5vHe6/i0HKSUgxOy66rzlwh73jRBcvBXiNNZpV3gim HEFdZ2HO0iVHOk0PYyXOZTznBFFmTN2Pjj0cQbzYLE86YaCsu1V568sgj3s7O3jAUukn Pf6oAY1UzE3UVDmRtHWL00eliVnydUTHD8uPb/3nPlY6ICP0ZX3HxzQw4PQ9Uao4vXAJ oLSPWX2Wbll7CmYEgjz+MdpNqc5ZCPRztGl4kppW2XGIN39VV/b7d5k+IdHSJ1TBfKrO AU1xeXzyX8L5ZeauijGIy7RA9ICA2j3WgReQu/9/ADpWxpuNlW+y9rWdPB/vvLEOJqXi wtUA== X-Gm-Message-State: ALoCoQkg8OOac3lzSDOVImAv7R69Q6Y9esaYGnDjEJR/5FNc5A+kbQybhtWUYbsBiC0MWfIF0QlQ X-Received: by 10.98.17.131 with SMTP id 3mr28434952pfr.57.1448429065990; Tue, 24 Nov 2015 21:24:25 -0800 (PST) Received: from localhost.localdomain ([106.192.41.229]) by smtp.gmail.com with ESMTPSA id s6sm17764154pfi.21.2015.11.24.21.24.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Nov 2015 21:24:25 -0800 (PST) From: Jassi Brar To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] clocksource: arm_global_timer: Allow DT to specify already reset timer counter Date: Wed, 25 Nov 2015 10:54:04 +0530 Message-Id: <1448429044-10395-1-git-send-email-jaswinder.singh@linaro.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151124_212448_301235_828455E6 X-CRM114-Status: GOOD ( 17.96 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux@arm.linux.org.uk, arnd@arndb.de, daniel.lezcano@linaro.org, Jassi Brar , srinivas.kandagatla@linaro.org, tglx@linutronix.de MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GT counter is common to every core in a cluster. There is a usecase when Linux is spawned by a 'master' firmware/OS running on some core of the same cluster and the GT is used by the both. Linux, upon boot, resetting the GT counter is obviously fatal to the other OS. So provide a way for DT to tell Linux if it's running in that 'slave' mode and must not reset the counter. Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/arm/global_timer.txt | 6 ++++++ drivers/clocksource/arm_global_timer.c | 12 +++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/global_timer.txt b/Documentation/devicetree/bindings/arm/global_timer.txt index bdae3a8..bb897a9 100644 --- a/Documentation/devicetree/bindings/arm/global_timer.txt +++ b/Documentation/devicetree/bindings/arm/global_timer.txt @@ -17,6 +17,12 @@ - clocks : Should be phandle to a clock. + +** Optional properties: + +- arm,gt_no_reset : Firmware/bootloader already initialized the + global timer-counter and expects it to be not reset again. + Example: timer@2c000600 { diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c index a2cb6fa..952bab6 100644 --- a/drivers/clocksource/arm_global_timer.c +++ b/drivers/clocksource/arm_global_timer.c @@ -51,6 +51,7 @@ static void __iomem *gt_base; static unsigned long gt_clk_rate; static int gt_ppi; static struct clock_event_device __percpu *gt_evt; +static bool gt_reset_counter; /* * To get the value from the Global Timer Counter register proceed as follows: @@ -212,9 +213,11 @@ static u64 notrace gt_sched_clock_read(void) static void __init gt_clocksource_init(void) { - writel(0, gt_base + GT_CONTROL); - writel(0, gt_base + GT_COUNTER0); - writel(0, gt_base + GT_COUNTER1); + if (gt_reset_counter) { + writel(0, gt_base + GT_CONTROL); + writel(0, gt_base + GT_COUNTER0); + writel(0, gt_base + GT_COUNTER1); + } /* enables timer on all the cores */ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); @@ -303,6 +306,9 @@ static void __init global_timer_of_register(struct device_node *np) goto out_irq; } + /* See if we are told we can't reset the global timer counter */ + gt_reset_counter = !of_property_read_bool(np, "arm,gt_no_reset"); + /* Immediately configure the timer on the boot CPU */ gt_clocksource_init(); gt_clockevents_init(this_cpu_ptr(gt_evt));