diff mbox

[v5,02/11] clk: rockchip: add mipidsi clocks on rk3288

Message ID 1448524225-5489-3-git-send-email-zyw@rock-chips.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chris Zhong Nov. 26, 2015, 7:50 a.m. UTC 
sclk_mipidsi_24m is the gating of mipi dsi phy.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>

---

Changes in v5:
- modify the mipidsi clk name to SCLK_MIPIDSI_24M

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Heiko Stübner Nov. 26, 2015, 1:58 p.m. UTC | #1 
Hi Chris,

Am Donnerstag, 26. November 2015, 15:50:16 schrieb Chris Zhong:
> sclk_mipidsi_24m is the gating of mipi dsi phy.
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

applied this to my clock branch for 4.5


Heiko
diff mbox

Patch

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 9040878..bee96e7 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -709,7 +709,7 @@  static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
 	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
-	GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
+	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
 
 	/* sclk_gpu gates */
 	GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),