From patchwork Wed Dec 2 17:22:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 7749731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E1DF5BEEE1 for ; Wed, 2 Dec 2015 17:25:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0DD86204D2 for ; Wed, 2 Dec 2015 17:25:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34D20204A2 for ; Wed, 2 Dec 2015 17:25:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4B7u-0004cq-1O; Wed, 02 Dec 2015 17:23:34 +0000 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4B7X-0004P9-J1 for linux-arm-kernel@lists.infradead.org; Wed, 02 Dec 2015 17:23:12 +0000 Received: by wmww144 with SMTP id w144so66436017wmw.0 for ; Wed, 02 Dec 2015 09:22:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=o1eMk3R0L2uqvW605bLyW10acpSXa+aIFVWIvBCsu6U=; b=a2eoXO8hiWI1i9Btkcewsgec092auQG/kdszlaerxlz7U0yLn9OdLthDducRozaYug BCLoFLu72hdXROiBJhJQDr746uz8p860sRa/BUHTuhofbnhcH+vWX8hqwGNdogjTPDxK cxe+4zMXmhclmEN/PL3/AeT2SJhqWui7Z/luRDQYCxQiLKSPxX6KfEWoM4TvglqqFv6R acQh0iZfT34aXYdW7cTgmlAeziApF+YK6MQM3OSnqZXBJz+LHt6Ibqo6eb44Y02+iAm6 NLz19p8ZN/0LTLJWaUbmzw1aATTh6oq2ggto370+e4o6y7pFrukBCRmKUzvjmLTG55ZL bGNQ== X-Received: by 10.28.194.135 with SMTP id s129mr43131702wmf.38.1449076970125; Wed, 02 Dec 2015 09:22:50 -0800 (PST) Received: from localhost.localdomain ([212.91.95.170]) by smtp.gmail.com with ESMTPSA id s189sm4111113wmf.16.2015.12.02.09.22.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 02 Dec 2015 09:22:49 -0800 (PST) From: Carlo Caione To: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux@arm.linux.org.uk, linux-meson@googlegroups.com, drake@endlessm.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, pawel.moll@arm.com, arnd@arndb.de Subject: [PATCH v2 2/7] dt-bindings: Amlogic: Document the CPU reset controller for Meson8b Date: Wed, 2 Dec 2015 18:22:28 +0100 Message-Id: <1449076953-5058-3-git-send-email-carlo@caione.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1449076953-5058-1-git-send-email-carlo@caione.org> References: <1449076953-5058-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151202_092311_894616_10610F99 X-CRM114-Status: GOOD ( 12.22 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlo Caione MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione The clock controller on Amlogic Meson8b SoCs has been extended with a reset controller used to reset the CPU cores. It is used during SMP bringup. With this patch we extend the clock controller documentation. Signed-off-by: Carlo Caione Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 2b7b3fa..feeb4de 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -1,7 +1,8 @@ * Amlogic Meson8b Clock and Reset Unit The Amlogic Meson8b clock controller generates and supplies clock to various -controllers within the SoC. +controllers within the SoC and also implements a reset controller for the CPU +cores. Required Properties: @@ -13,16 +14,19 @@ Required Properties: mapped region. - #clock-cells: should be 1. +- #reset-cells: should be 1. Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be used in device tree sources. +Similar identifiers exist for the CPU core reset lines. Example: Clock controller node: clkc: clock-controller@c1104000 { #clock-cells = <1>; + #reset-cells = <1>; compatible = "amlogic,meson8b-clkc"; reg = <0xc1108000 0x4>, <0xc1104000 0x460>; };