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[4/4] ARM: dts: sun9i: Add NMI controller device node

Message ID 1449130813-22400-5-git-send-email-wens@csie.org (mailing list archive)
State New, archived
Headers show

Commit Message

Chen-Yu Tsai Dec. 3, 2015, 8:20 a.m. UTC 
The Allwinner A80 SoC has an NMI controller. NMI is an external
interrupt pin exclusely used with PMICs and other system critical
peripherals (such as RTC) in Allwinner's reference designs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Maxime Ripard Dec. 3, 2015, 9:46 a.m. UTC | #1 
On Thu, Dec 03, 2015 at 04:20:13PM +0800, Chen-Yu Tsai wrote:
> The Allwinner A80 SoC has an NMI controller. NMI is an external
> interrupt pin exclusely used with PMICs and other system critical
> peripherals (such as RTC) in Allwinner's reference designs.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index dc666c69f6ab..e838f206f2a0 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -858,6 +858,14 @@ 
 			#reset-cells = <1>;
 		};
 
+		nmi_intc: interrupt-controller@080015a0 {
+			compatible = "allwinner,sun9i-a80-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x080015a0 0xc>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		r_ir: ir@08002000 {
 			compatible = "allwinner,sun5i-a13-ir";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;