| Message ID | 1449316424-14549-2-git-send-email-kapilh@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali <kapilh@broadcom.com> Applied to devicetree/next, thanks!
On Sat, Dec 05, 2015 at 06:53:40AM -0500, Kapil Hali wrote: > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali <kapilh@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> > --- > .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++ > Documentation/devicetree/bindings/arm/cpus.txt | 1 + > 2 files changed, 40 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > > diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > new file mode 100644 > index 0000000..677ef9d > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > @@ -0,0 +1,39 @@ > +Broadcom Northstar Plus SoC CPU Enable Method > +--------------------------------------------- > +This binding defines the enable method used for starting secondary > +CPU in the following Broadcom SoCs: > + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 > + > +The enable method is specified by defining the following required > +properties in the corresponding secondary "cpu" device tree node: > + - enable-method = "brcm,bcm-nsp-smp"; > + - secondary-boot-reg = <...>; > + > +The secondary-boot-reg property is a u32 value that specifies the > +physical address of the register which should hold the common > +entry point for a secondary CPU. This entry is cpu node specific > +and should be added per cpu. E.g., in case of NSP (BCM58625) which > +is a dual core CPU SoC, this entry should be added to cpu1 node. > + > + > +Example: > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + next-level-cache = <&L2>; > + reg = <0>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + next-level-cache = <&L2>; > + enable-method = "brcm,bcm-nsp-smp"; > + secondary-boot-reg = <0xffff042c>; > + reg = <1>; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > index 3a07a87..d191554 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.txt > +++ b/Documentation/devicetree/bindings/arm/cpus.txt > @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below. > "allwinner,sun6i-a31" > "allwinner,sun8i-a23" > "arm,psci" > + "brcm,bcm-nsp-smp" > "brcm,brahma-b15" > "marvell,armada-375-smp" > "marvell,armada-380-smp" > -- > 2.1.0 >
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file mode 100644 index 0000000..677ef9d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt @@ -0,0 +1,39 @@ +Broadcom Northstar Plus SoC CPU Enable Method +--------------------------------------------- +This binding defines the enable method used for starting secondary +CPU in the following Broadcom SoCs: + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 + +The enable method is specified by defining the following required +properties in the corresponding secondary "cpu" device tree node: + - enable-method = "brcm,bcm-nsp-smp"; + - secondary-boot-reg = <...>; + +The secondary-boot-reg property is a u32 value that specifies the +physical address of the register which should hold the common +entry point for a secondary CPU. This entry is cpu node specific +and should be added per cpu. E.g., in case of NSP (BCM58625) which +is a dual core CPU SoC, this entry should be added to cpu1 node. + + +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + enable-method = "brcm,bcm-nsp-smp"; + secondary-boot-reg = <0xffff042c>; + reg = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87..d191554 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below. "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,psci" + "brcm,bcm-nsp-smp" "brcm,brahma-b15" "marvell,armada-375-smp" "marvell,armada-380-smp"
Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU. Signed-off-by: Kapil Hali <kapilh@broadcom.com> --- .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt