From patchwork Mon Dec 7 18:18:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 7788921 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B8E4E9F39B for ; Mon, 7 Dec 2015 18:23:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A2C6D20557 for ; Mon, 7 Dec 2015 18:23:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 863302054E for ; Mon, 7 Dec 2015 18:23:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a60P7-00085O-V5; Mon, 07 Dec 2015 18:20:53 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a60OM-0006Lx-Hb for linux-arm-kernel@lists.infradead.org; Mon, 07 Dec 2015 18:20:08 +0000 Received: from epcpsbgm2new.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ001LLO2WWTX90@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 03:19:44 +0900 (KST) X-AuditID: cbfee61b-f793c6d00000236c-14-5665cdc00b4e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 11.3D.09068.0CDC5665; Tue, 8 Dec 2015 03:19:44 +0900 (KST) Received: from AMDC1976.DIGITAL.local ([106.120.53.102]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ000I0K2W6PR40@mmp2.samsung.com>; Tue, 08 Dec 2015 03:19:44 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski , Ben Gamari Subject: [PATCH v4 2/8] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock Date: Mon, 07 Dec 2015 19:18:14 +0100 Message-id: <1449512300-17230-3-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1449512300-17230-1-git-send-email-b.zolnierkie@samsung.com> References: <1449512300-17230-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsVy+t9jQd0DZ1PDDC7PE7TYOGM9q8Ws+XdZ LK5/ec5q8f/Ra1aLo78LLN68XcNk8fqFoUXvgqtsFv2PXzNbfD28gtHizcPNjBabHl9jtbi8 aw6bxefeI4wWM87vY7JYt/EWu8XTCRfZLA6/aWe16FjGaNG2+gOrxapdfxgtNn71cBDz+Pv8 OovHzll32T02repk87hzbQ+bx+Yl9R7/jrF7bOkHCvdtWcXocea3s8f2a/OYPT5vkgvgjuKy SUnNySxLLdK3S+DKmDZxA3PBDbWKxT96WBsYGxW6GDk5JARMJJat+coMYYtJXLi3nq2LkYtD SGAWo8ScQ7+YIJxfjBIvlkxmBaliE7CSmNi+ihEkISJwjEniUetNdhCHWWAli8SGfTfZQKqE BfIkrj55xNLFyMHBIqAq0d1QAxLmFfCQONW3AmqdnMTJYxBDOQU8Ja68XQdmCwHVrNz+knUC I+8CRoZVjBKpBckFxUnpuUZ5qeV6xYm5xaV56XrJ+bmbGMEx8kx6B+PhXe6HGAU4GJV4eE8c Sw0TYk0sK67MPcQowcGsJMIrmwkU4k1JrKxKLcqPLyrNSS0+xCjNwaIkzrvvUmSYkEB6Yklq dmpqQWoRTJaJg1OqgVGRN/fYryc1X2fY7zazDGNwsJup8N23455a9qYnfq+nrX4kFRy0udx1 fcHqDQ7TJB5Otpp0dttKzzN+Hota3rQ92HR1k6z1w3nX7mmeiYoXNa7eLXNRfa21uMp+fmkd A3MRU/YpFdwlz3gCXnnoG15+E9eaphSRIMDrd+T5K2b3rxIZd7vS1yuxFGckGmoxFxUnAgCs xX4rjQIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151207_102006_953082_C25BC6DD X-CRM114-Status: GOOD ( 15.52 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lukasz Majewski , Kevin Hilman , Heiko Stuebner , Javier Martinez Canillas , Anand Moon , linux-pm@vger.kernel.org, Tomasz Figa , linux-kernel@vger.kernel.org, Chanwoo Choi , b.zolnierkie@samsung.com, Tobias Jakobi , linux-arm-kernel@lists.infradead.org, Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5420. Changes by Bartlomiej: - split Exynos5420 support from the original patches - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Acked-by: Sylwester Nawrocki Signed-off-by: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/clk/samsung/clk-exynos5420.c | 58 ++++++++++++++++++++++++++++++++-- include/dt-bindings/clock/exynos5420.h | 2 ++ 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 389af3c..2a92546 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -18,6 +18,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), + MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), @@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { KPLL_CON0, NULL), }; +#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ + ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((cpud) << 4))) + +static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, + { 0 }, +}; + +#define E5420_KFC_DIV(kpll, pclk, aclk) \ + ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) + +static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1300000, E5420_KFC_DIV(3, 5, 2), }, + { 1200000, E5420_KFC_DIV(3, 5, 2), }, + { 1100000, E5420_KFC_DIV(3, 5, 2), }, + { 1000000, E5420_KFC_DIV(3, 5, 2), }, + { 900000, E5420_KFC_DIV(3, 5, 2), }, + { 800000, E5420_KFC_DIV(3, 5, 2), }, + { 700000, E5420_KFC_DIV(3, 4, 2), }, + { 600000, E5420_KFC_DIV(3, 4, 2), }, + { 500000, E5420_KFC_DIV(3, 4, 2), }, + { 400000, E5420_KFC_DIV(3, 3, 2), }, + { 300000, E5420_KFC_DIV(3, 3, 2), }, + { 200000, E5420_KFC_DIV(3, 3, 2), }, + { 0 }, +}; + static const struct of_device_id ext_clk_match[] __initconst = { { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, { }, @@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", + mout_kfc_p[0], mout_kfc_p[1], 0x28200, + exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); + exynos5420_clk_sleep_init(); samsung_clk_of_add_provider(np, ctx); diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 99da0d1..dde9664 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -25,6 +25,8 @@ #define CLK_FOUT_MPLL 10 #define CLK_FOUT_BPLL 11 #define CLK_FOUT_KPLL 12 +#define CLK_ARM_CLK 13 +#define CLK_KFC_CLK 14 /* gate for special clocks (sclk) */ #define CLK_SCLK_UART0 128