From patchwork Thu Dec 10 05:33:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Ulli Kroll X-Patchwork-Id: 7814651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C8E549F349 for ; Thu, 10 Dec 2015 05:37:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B2CEB20547 for ; Thu, 10 Dec 2015 05:37:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23E102053D for ; Thu, 10 Dec 2015 05:37:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6tsN-0002tt-4m; Thu, 10 Dec 2015 05:34:47 +0000 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6tsK-0002sW-39 for linux-arm-kernel@lists.infradead.org; Thu, 10 Dec 2015 05:34:45 +0000 Received: by mail-wm0-x233.google.com with SMTP id c201so15874708wme.0 for ; Wed, 09 Dec 2015 21:34:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=cpORNGaVwkOlkx305k3Zp4IuGFpxs5XrU+HIKclRjrs=; b=0NBdbu3B+e2OmnbYZDKQ0we9GAEk1eGVHh/MxlleWYetoRxXYWeV9vx8mT9J2yTPYU 3QzI4i9LeOQbwiHCNNDLFijjhKtXh3fnOafegE/iuUayS2nAQ52+dBszvVho5Ba3aCly ijImFJ7Zra8rlhlJ2c4LhcFstQ9ONlsnllfwxBptoJTGdM0LjvPE7ntxauvWvI5y1zYl DYQ8rmqFr7/3/2hsvcBosQfruKIxsIh+e2BACUjW8e6Le/RitYbccLVCC1zjdJhcXUJF +OEqNd2hvea3PaxytzgKwjALPTGKPyJIyv0VduEoF/pxdExvCB3A8C5ozwxOS3XRXy2a ziIw== X-Received: by 10.194.223.39 with SMTP id qr7mr9996904wjc.63.1449725662332; Wed, 09 Dec 2015 21:34:22 -0800 (PST) Received: from localhost (ip-109-44-0-93.web.vodafone.de. [109.44.0.93]) by smtp.gmail.com with ESMTPSA id q4sm10650030wja.6.2015.12.09.21.34.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Dec 2015 21:34:21 -0800 (PST) From: Hans Ulli Kroll To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Subject: [PATCHv2] ARM: dts: kirkwood: Add DTS for Zyxel NSA325 Date: Thu, 10 Dec 2015 06:33:08 +0100 Message-Id: <1449725588-9438-1-git-send-email-ulli.kroll@googlemail.com> X-Mailer: git-send-email 2.6.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151209_213444_431880_B839ACFA X-CRM114-Status: GOOD ( 18.67 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hans Ulli Kroll , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a new DTS file to support the Zyxel NSA325(v2) dual bay NAS device, based on the NSA320 DTS files. The only difference to the NSA320 device is GPIO47. This en/disables the power for the hdd in slot2, currently fixed to on. Signed-off-by: Hans Ulli Kroll Acked-by: Andrew Lunn --- v2 - using kirkwood-nsa325.dts as template, this removes the odd indentation and unneeded partitions nodes. arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-nsa325.dts | 236 ++++++++++++++++++++++++++++++++++ 2 files changed, 237 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-nsa325.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bb8fa02..0fcae90 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -193,6 +193,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ kirkwood-nsa310a.dtb \ + kirkwood-nsa325.dtb \ kirkwood-openblocks_a6.dtb \ kirkwood-openblocks_a7.dtb \ kirkwood-openrd-base.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/kirkwood-nsa325.dts new file mode 100644 index 0000000..6e9ffb5 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa325.dts @@ -0,0 +1,236 @@ +/* Device tree file for the Zyxel NSA 325 NAS box. + * + * Copyright (c) 2015, Hans Ulli Kroll + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Based upon the board setup file created by Peter Schildmann */ + +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/ { + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_hdd2_green: pmx-led-hdd2-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_hdd2_red: pmx-led-hdd2-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_mcu_data: pmx-mcu-data { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_mcu_clk: pmx-mcu-clk { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_mcu_act: pmx-mcu-act { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_orange: pmx-led-sys-orange { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_green: pmx-led-hdd1-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_red: pmx-led-hdd1-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_htp: pmx-htp { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + /* Buzzer needs to be switched at around 1kHz so is + not compatible with the gpio-beeper driver. */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_vid_b1: pmx-vid-b1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_resume_data: pmx-power-resume-data { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_power_resume_clk: pmx-power-resume-clk { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + + pmx_pwr_sata1: pmx-pwr-sata1 { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + /* This board uses the pcf8563 RTC instead of the SoC RTC */ + rtc@10300 { + status = "disabled"; + }; + + i2c@11000 { + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_pwr_sata1>; + pinctrl-names = "default"; + + usb0_power: regulator@1 { + enable-active-high; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red + &pmx_led_usb_green + &pmx_led_sys_green &pmx_led_sys_orange + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa325:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd1 { + label = "nsa325:red:hdd1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-hdd2 { + label = "nsa325:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-hdd2 { + label = "nsa325:red:hdd2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa325:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa325:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa325:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + /* The following pins are currently not assigned to a driver, + some of them should be configured as inputs. + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act + &pmx_htp &pmx_vid_b1 + &pmx_power_resume_data &pmx_power_resume_clk>; */ + + }; + + +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; +