From patchwork Fri Dec 11 09:55:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "tiffany.lin" X-Patchwork-Id: 7827901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B6CE69F6CD for ; Fri, 11 Dec 2015 09:58:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD8FB20460 for ; Fri, 11 Dec 2015 09:58:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 061D520562 for ; Fri, 11 Dec 2015 09:58:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a7KRZ-0008RG-1I; Fri, 11 Dec 2015 09:56:53 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a7KR4-00086u-JG; Fri, 11 Dec 2015 09:56:23 +0000 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 475893800; Fri, 11 Dec 2015 17:55:56 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 11 Dec 2015 17:55:55 +0800 From: Tiffany Lin To: , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Mauro Carvalho Chehab , Matthias Brugger , Daniel Kurtz , Hans Verkuil , Laurent Pinchart , Sakari Ailus , Mikhail Ulyanov , Fabien Dessenne , Arnd Bergmann , Darren Etheridge , Peter Griffin , Benoit Parrot Subject: [PATCH v2 5/8] arm64: dts: mediatek: Add Video Encoder for MT8173 Date: Fri, 11 Dec 2015 17:55:40 +0800 Message-ID: <1449827743-22895-6-git-send-email-tiffany.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1449827743-22895-1-git-send-email-tiffany.lin@mediatek.com> References: <1449827743-22895-1-git-send-email-tiffany.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151211_015622_783653_B73C8451 X-CRM114-Status: GOOD ( 14.02 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Eddie Huang , Daniel Hsiao , Andrew-CT Chen , Hongzhou Yang , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, PoChun.Lin@mediatek.com, Yingjoe Chen , Tiffany Lin , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add video encoder node for MT8173 Signed-off-by: Tiffany Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 47 ++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index b8c8ff0..a6b0fcf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -545,6 +545,53 @@ #clock-cells = <1>; }; + larb3: larb@18001000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_CKE1>, + <&vencsys CLK_VENC_CKE0>; + clock-names = "apb", "smi"; + }; + + vcodec_enc: vcodec@18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ + <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = , + ; + larb = <&larb3>, + <&larb5>; + iommus = <&iommu M4U_LARB3_ID M4U_PORT_VENC_RCPU>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REC>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_BSDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_CHROMA_SET2>; + vpu = <&vpu>; + clocks = <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vencpll", + "venc_lt_sel", + "vcodecpll_370p5_ck"; + }; + vencltsys: clock-controller@19000000 { compatible = "mediatek,mt8173-vencltsys", "syscon"; reg = <0 0x19000000 0 0x1000>;