From patchwork Thu Dec 17 01:37:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 7868311 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 09DF69F350 for ; Thu, 17 Dec 2015 01:39:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 274042022D for ; Thu, 17 Dec 2015 01:39:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5304D20225 for ; Thu, 17 Dec 2015 01:39:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9NWE-0005XW-Ne; Thu, 17 Dec 2015 01:38:10 +0000 Received: from mail-ob0-x22f.google.com ([2607:f8b0:4003:c01::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9NWA-0005UC-QJ for linux-arm-kernel@lists.infradead.org; Thu, 17 Dec 2015 01:38:07 +0000 Received: by mail-ob0-x22f.google.com with SMTP id sd4so47159255obb.0 for ; Wed, 16 Dec 2015 17:37:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id; bh=Lu9OCNFD9IW1FV25RsfMO175F12AxO4nLNgkZIIbufU=; b=r/cxaOfFs704TgnCBD6BbuNoTTZlswPGXlNgXdLlWAmf7wPDAG2buw7+CgxBn3jPlU nnqG2P3hq0NVlUVGhqgrUyFeM5v/pwrEw+YFMT39CybNcHO20MOXGMMDddriRDQuHNO0 uMsVKKCstLH3u7IM0CqVb6GTcK2U456RU8mgo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Lu9OCNFD9IW1FV25RsfMO175F12AxO4nLNgkZIIbufU=; b=WCNwcR+tTq7R0pOSCC1G73bvIY7vvvDiAF1CX0imrHRGYYP4FkZ0JROGQJaEePsQBv FWkeVCQCVvPIO36hsMiUBjPB+cVTRzBcjs/ls1nyTxNmY4Ny8dMJdS6q3AYY5cHvMHKq aR2fs7Wizx48tQuC0zKySM74I+5Tqdrx8HbxmYVZ+FykDmEuBAQS4Ty829X3sn67YKae ASAVRLjWzLg5sVe+SYdbGw+3Y2wvFB93PMKRakGm2sOYtKKVTuvuZIAOni3M91SWY3VV U1HKrN9BAWshuktEgRixkVQxPHnm5pTWVqalGz8OPIe6fD2wj7GI8fmD18qm+fE889Lg HOpA== X-Gm-Message-State: ALoCoQnIRZIpA7exXB6eXw3+xmFV5Z035W3EayjF2rZz1gWzprg697ewVzN2z6QbG88CchkzWidrP8fhN9IAaTAe/DeEYyMyvg== X-Received: by 10.182.165.67 with SMTP id yw3mr29376910obb.45.1450316265216; Wed, 16 Dec 2015 17:37:45 -0800 (PST) Received: from localhost.localdomain ([198.137.200.11]) by smtp.gmail.com with ESMTPSA id kw1sm2742157obb.28.2015.12.16.17.37.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Dec 2015 17:37:43 -0800 (PST) From: Loc Ho To: mturquette@baylibre.com, sboyd@codeaurora.org Subject: [PATCH] clk: xgene: Add SoC and PMD PLL clocks with v2 hardware Date: Wed, 16 Dec 2015 18:37:35 -0700 Message-Id: <1450316255-9372-1-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.7.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151216_173806_957457_3C73FB9E X-CRM114-Status: GOOD ( 13.83 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@apm.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loc Ho MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic. Signed-off-by: Loc Ho --- drivers/clk/clk-xgene.c | 57 ++++++++++++++++++++++++++++++++-------------- 1 files changed, 39 insertions(+), 18 deletions(-) diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index 8131ccf..0f446d3 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -27,9 +27,12 @@ #include #include #include +#include /* Register SCU_PCPPLL bit fields */ -#define N_DIV_RD(src) (((src) & 0x000001ff)) +#define N_DIV_RD(src) ((src) & 0x000001ff) +#define SC_N_DIV_RD(src) ((src) & 0x0000007f) +#define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8) /* Register SCU_SOCPLL bit fields */ #define CLKR_RD(src) (((src) & 0x07000000)>>24) @@ -41,6 +44,14 @@ static DEFINE_SPINLOCK(clk_lock); +static int xgene_clk_version(void) +{ + #define MIDR_EL1_VARIANT_MASK 0x00f00000 + u32 val = read_cpuid_id(); + + return (val & MIDR_EL1_VARIANT_MASK) == 0 ? 1 : 2; +} + static inline u32 xgene_clk_read(void __iomem *csr) { return readl_relaxed(csr); @@ -92,27 +103,37 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); - if (pllclk->type == PLL_TYPE_PCP) { - /* - * PLL VCO = Reference clock * NF - * PCP PLL = PLL_VCO / 2 - */ - nout = 2; - fvco = parent_rate * (N_DIV_RD(pll) + 4); + if (xgene_clk_version() <= 1) { + if (pllclk->type == PLL_TYPE_PCP) { + /* + * PLL VCO = Reference clock * NF + * PCP PLL = PLL_VCO / 2 + */ + nout = 2; + fvco = parent_rate * (N_DIV_RD(pll) + 4); + } else { + /* + * Fref = Reference Clock / NREF; + * Fvco = Fref * NFB; + * Fout = Fvco / NOUT; + */ + nref = CLKR_RD(pll) + 1; + nout = CLKOD_RD(pll) + 1; + nfb = CLKF_RD(pll); + fref = parent_rate / nref; + fvco = fref * nfb; + } } else { /* - * Fref = Reference Clock / NREF; - * Fvco = Fref * NFB; - * Fout = Fvco / NOUT; + * fvco = Reference clock * FBDIVC + * PLL freq = fvco / NOUT */ - nref = CLKR_RD(pll) + 1; - nout = CLKOD_RD(pll) + 1; - nfb = CLKF_RD(pll); - fref = parent_rate / nref; - fvco = fref * nfb; + nout = SC_OUTDIV2(pll) ? 2 : 3; + fvco = parent_rate * SC_N_DIV_RD(pll); } - pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw), - fvco / nout, parent_rate); + pr_debug("%s pll recalc rate %ld parent %ld version %d\n", + clk_hw_get_name(hw), fvco / nout, parent_rate, + xgene_clk_version()); return fvco / nout; }