From patchwork Wed Dec 23 02:22:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 7908571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C41DD9F32E for ; Wed, 23 Dec 2015 02:25:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED5C12041C for ; Wed, 23 Dec 2015 02:25:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 208FE20431 for ; Wed, 23 Dec 2015 02:25:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aBZ5z-00025j-Qq; Wed, 23 Dec 2015 02:24:07 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aBZ5w-0001zT-Fv for linux-arm-kernel@lists.infradead.org; Wed, 23 Dec 2015 02:24:05 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F40B2041E; Wed, 23 Dec 2015 02:23:41 +0000 (UTC) Received: from localhost.localdomain (unknown [58.209.137.190]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6515A2041C; Wed, 23 Dec 2015 02:23:38 +0000 (UTC) From: Shawn Guo To: arm@kernel.org Subject: [PATCH] ARM: dts: imx6q: clean up unused ipu2grp Date: Wed, 23 Dec 2015 10:22:57 +0800 Message-Id: <1450837377-23103-1-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151222_182404_638140_94ECF034 X-CRM114-Status: GOOD ( 12.70 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Michael Trimarchi , Shawn Guo , kernel@pengutronix.de, Akshay Bhat MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The pinctrl group ipu2grp is a leftover from the previous iomuxc DT cleanup. It's not used by anyone now. More importantly, it's getting in the way of saving the unnecessary pinfunc container node from the board dts files that include imx6q.dtsi. Let's clean it up. Signed-off-by: Shawn Guo Tested-by: Michael Trimarchi --- Hi arm-soc folks, Olof just merged my 4.5 pull requests (thanks). And here is one cleanup patch, which will be quite useful for imx6q board files we are going to add in the next development cycle. It helps to save the pinfunc container node and thus one level of indentation from board dts. So please apply it to arm-soc for 4.5 merge window. Thanks. Shawn arch/arm/boot/dts/imx6q.dtsi | 36 ------------------------------------ 1 file changed, 36 deletions(-) diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9b6a193b64ca..0d93c0e8f9ba 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -104,42 +104,6 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; - - ipu2 { - pinctrl_ipu2_1: ipu2grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 - MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 - >; - }; - }; }; };