From patchwork Tue Jan 19 02:38:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 8057801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A986BBF0A9 for ; Tue, 19 Jan 2016 02:54:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93590203C1 for ; Tue, 19 Jan 2016 02:54:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E903720445 for ; Tue, 19 Jan 2016 02:54:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aLMPE-0007Gr-EC; Tue, 19 Jan 2016 02:52:28 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aLMOr-0007BF-0J for linux-arm-kernel@lists.infradead.org; Tue, 19 Jan 2016 02:52:08 +0000 Received: from 172.24.1.48 (EHLO szxeml427-hub.china.huawei.com) ([172.24.1.48]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAC92370; Tue, 19 Jan 2016 10:51:01 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by szxeml427-hub.china.huawei.com (10.82.67.182) with Microsoft SMTP Server id 14.3.235.1; Tue, 19 Jan 2016 10:50:48 +0800 From: Jiancheng Xue To: , , , , , , , , , , , , , , , Subject: [PATCH v6 6/6] ARM: dts: add dts files for Hi3519 Date: Tue, 19 Jan 2016 10:38:31 +0800 Message-ID: <1453171111-21921-7-git-send-email-xuejiancheng@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453171111-21921-1-git-send-email-xuejiancheng@huawei.com> References: <1453171111-21921-1-git-send-email-xuejiancheng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.569DA497.00FA, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9dcb23702f05563f859e0c841c9217d2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160118_185205_694134_D0635670 X-CRM114-Status: GOOD ( 16.38 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suwenping@hisilicon.com, devicetree@vger.kernel.org, yanhaifeng@hisilicon.com, linux-kernel@vger.kernel.org, raojun@hisilicon.com, xuejiancheng@hisilicon.com, gaofei@hisilicon.com, Jiancheng Xue , ml.yang@hisilicon.com, yanghongwei@hisilicon.com, zhangzhenxing@hisilicon.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP add dts files for Hi3519 Signed-off-by: Jiancheng Xue --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3519-demb.dts | 42 +++++++++ arch/arm/boot/dts/hi3519.dtsi | 187 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 arch/arm/boot/dts/hi3519-demb.dts create mode 100644 arch/arm/boot/dts/hi3519.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30bbc37..1ff3ed9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_HI3xxx) += \ hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HISI) += \ + hi3519-demb.dtb dtb-$(CONFIG_ARCH_HIX5HD2) += \ hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += \ diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts new file mode 100644 index 0000000..6991ab6 --- /dev/null +++ b/arch/arm/boot/dts/hi3519-demb.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +/dts-v1/; +#include "hi3519.dtsi" + +/ { + model = "HiSilicon HI3519 DEMO Board"; + compatible = "hisilicon,hi3519"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&dual_timer0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi new file mode 100644 index 0000000..5729ecf --- /dev/null +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + }; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10301000 0x1000>, <0x10302000 0x1000>; + }; + + clk_3m: clk_3m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + + crg: clock-reset-controller@12010000 { + compatible = "hisilicon,hi3519-crg"; + #clock-cells = <1>; + #reset-cells = <2>; + reg = <0x12010000 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@12100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12100000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart1: serial@12101000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12101000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART1_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart2: serial@12102000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12102000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart3: serial@12103000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12103000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART3_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart4: serial@12104000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12104000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART4_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer0: timer@12000000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12000000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer1: timer@12001000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12001000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer2: timer@12002000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12002000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + spi_bus0: spi@12120000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12120000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI0_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus1: spi@12121000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12121000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI1_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus2: spi@12122000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12122000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI2_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + sysctrl: system-controller@12020000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12020000 0x1000>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; + }; + }; +};