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[v2,1/3] Documentation: Update APM X-Gene clock binding for v2 hardware

Message ID 1453256863-15092-2-git-send-email-lho@apm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Loc Ho Jan. 20, 2016, 2:27 a.m. UTC
Update APM X-Gene clock binding documentation for SoC and
PCP PLL for v2 hardware.

Signed-off-by: Loc Ho <lho@apm.com>
---
 Documentation/devicetree/bindings/clock/xgene.txt |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

Comments

Stephen Boyd Jan. 30, 2016, 12:33 a.m. UTC | #1
On 01/19, Loc Ho wrote:
> Update APM X-Gene clock binding documentation for SoC and
> PCP PLL for v2 hardware.
> 
> Signed-off-by: Loc Ho <lho@apm.com>
> ---

Applied to clk-next
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Patch

diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt
index 1c4ef77..3fe3169 100644
--- a/Documentation/devicetree/bindings/clock/xgene.txt
+++ b/Documentation/devicetree/bindings/clock/xgene.txt
@@ -9,6 +9,8 @@  Required properties:
 	"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
 	"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
 	"apm,xgene-device-clock" - for a X-Gene device clock
+	"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
+	"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
 
 Required properties for SoC or PCP PLL clocks:
 - reg : shall be the physical PLL register address for the pll clock.