From patchwork Thu Jan 21 05:26:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 8078371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 67C90BEEE5 for ; Thu, 21 Jan 2016 05:41:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 84D1B205BB for ; Thu, 21 Jan 2016 05:41:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8EAB9205B7 for ; Thu, 21 Jan 2016 05:41:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aM7ys-0004XX-Eb; Thu, 21 Jan 2016 05:40:26 +0000 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aM7t3-0005TH-Q5 for linux-arm-kernel@lists.infradead.org; Thu, 21 Jan 2016 05:34:34 +0000 Received: from mirror2.csie.ntu.edu.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (Authenticated sender: b93043) by smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id E625624F66; Thu, 21 Jan 2016 13:33:30 +0800 (CST) Received: by mirror2.csie.ntu.edu.tw (Postfix, from userid 1000) id B48FA5F9BC; Thu, 21 Jan 2016 13:33:30 +0800 (CST) From: Chen-Yu Tsai To: Ulf Hansson , Maxime Ripard Subject: [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Date: Thu, 21 Jan 2016 13:26:33 +0800 Message-Id: <1453354002-28366-7-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1453354002-28366-1-git-send-email-wens@csie.org> References: <1453354002-28366-1-git-send-email-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160120_213426_464161_6794A0AE X-CRM114-Status: GOOD ( 12.70 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mmc@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Hans de Goede , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner's MMC controller needs to run at double the card clock rate for 8 bit DDR transfer modes. Interestingly, this is not needed for 4 bit DDR transfers. Different clock delays are needed for 8 bit eMMC DDR, due to the increased module clock rate. For the A80 though, the same values for 4 bit and 8 bit are shared. The new values for the other SoCs were from A83T user manual's "new timing mode" default values, which describes them in clock phase, rather than delay periods. These values were used without any modification. They may not be correct, but they work. Signed-off-by: Chen-Yu Tsai --- drivers/mmc/host/sunxi-mmc.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index b403a2433eec..d05928091b34 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -215,6 +215,7 @@ #define SDXC_CLK_25M 1 #define SDXC_CLK_50M 2 #define SDXC_CLK_50M_DDR 3 +#define SDXC_CLK_50M_DDR_8BIT 4 struct sunxi_mmc_clk_delay { u32 output; @@ -656,11 +657,17 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, struct mmc_ios *ios) { u32 rate, oclk_dly, rval, sclk_dly; + u32 clock = ios->clock; int ret; - rate = clk_round_rate(host->clk_mmc, ios->clock); + /* 8 bit DDR requires a higher module clock */ + if (ios->timing == MMC_TIMING_MMC_DDR52 && + ios->bus_width == MMC_BUS_WIDTH_8) + clock <<= 1; + + rate = clk_round_rate(host->clk_mmc, clock); dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n", - ios->clock, rate); + clock, rate); /* setting clock rate */ ret = clk_set_rate(host->clk_mmc, rate); @@ -677,6 +684,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, /* clear internal divider */ rval = mmc_readl(host, REG_CLKCR); rval &= ~0xff; + /* set internal divider for 8 bit eMMC DDR, so card clock is right */ + if (ios->timing == MMC_TIMING_MMC_DDR52 && + ios->bus_width == MMC_BUS_WIDTH_8) { + rval |= 1; + rate >>= 1; + } mmc_writel(host, REG_CLKCR, rval); /* determine delays */ @@ -687,13 +700,16 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, oclk_dly = host->clk_delays[SDXC_CLK_25M].output; sclk_dly = host->clk_delays[SDXC_CLK_25M].sample; } else if (rate <= 50000000) { - if (ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_DDR52) { - oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output; - sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample; - } else { + if (ios->timing != MMC_TIMING_UHS_DDR50 && + ios->timing != MMC_TIMING_MMC_DDR52) { oclk_dly = host->clk_delays[SDXC_CLK_50M].output; sclk_dly = host->clk_delays[SDXC_CLK_50M].sample; + } else if (ios->bus_width == MMC_BUS_WIDTH_8) { + oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output; + sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample; + } else { + oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output; + sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample; } } else { return -EINVAL; @@ -965,6 +981,8 @@ static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, + /* Value from A83T "new timing mode". Works but might not be right. */ + [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, }; static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { @@ -972,6 +990,7 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 }, + [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 120 }, }; static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,