From patchwork Wed Jan 27 16:13:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tthayer@opensource.altera.com X-Patchwork-Id: 8135401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3B90ABEEE5 for ; Wed, 27 Jan 2016 16:12:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 656F420270 for ; Wed, 27 Jan 2016 16:12:36 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8093120221 for ; Wed, 27 Jan 2016 16:12:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aOSg7-0003R3-Ic; Wed, 27 Jan 2016 16:10:43 +0000 Received: from mail-bn1bon0091.outbound.protection.outlook.com ([157.56.111.91] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aOSfm-0001rd-Tv for linux-arm-kernel@lists.infradead.org; Wed, 27 Jan 2016 16:10:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.onmicrosoft.com; s=selector1-opensource-altera-com; h=From:To:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=O+XD4k8jnQpGJrPa4Q25S7++ZqfA1ZwB4a3B0Q8fHpI=; b=a7+sb1GkGS4NZcB1QZR5cwJvr94Q+96MBzv45+TtxETw/ER/LApaioH0zNz2CpxWO4fkxxifhYZRmWooOTxasFf0bbyjywRqhoqnX7ikdBimemmfo/0EN8LgO6ld+IIgZ1SbHP2VmrY5h9qqeOPfDJgOtSV5m3GY5aAe9sRaU/4= Received: from DM2PR03CA0006.namprd03.prod.outlook.com (10.141.96.16) by CY1PR0301MB1308.namprd03.prod.outlook.com (10.161.212.18) with Microsoft SMTP Server (TLS) id 15.1.365.19; Wed, 27 Jan 2016 16:09:59 +0000 Received: from BN1BFFO11FD005.protection.gbl (2a01:111:f400:7c10::1:150) by DM2PR03CA0006.outlook.office365.com (2a01:111:e400:2428::16) with Microsoft SMTP Server (TLS) id 15.1.396.15 via Frontend Transport; Wed, 27 Jan 2016 16:09:58 +0000 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=pass (signature was verified) header.d=altera.onmicrosoft.com; vger.kernel.org; dmarc=none action=none header.from=opensource.altera.com; Received-SPF: Fail (protection.outlook.com: domain of opensource.altera.com does not designate 66.35.236.236 as permitted sender) receiver=protection.outlook.com; client-ip=66.35.236.236; helo=sj-itexedge04.altera.priv.altera.com; Received: from sj-itexedge04.altera.priv.altera.com (66.35.236.236) by BN1BFFO11FD005.mail.protection.outlook.com (10.58.144.68) with Microsoft SMTP Server (TLS) id 15.1.355.15 via Frontend Transport; Wed, 27 Jan 2016 16:09:57 +0000 Received: from na01-bn1-obe.outbound.protection.outlook.com (207.46.163.142) by webmail.altera.com (66.35.236.236) with Microsoft SMTP Server (TLS) id 14.3.174.1; Wed, 27 Jan 2016 08:08:58 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.onmicrosoft.com; s=selector1-opensource-altera-com; h=From:To:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=O+XD4k8jnQpGJrPa4Q25S7++ZqfA1ZwB4a3B0Q8fHpI=; b=a7+sb1GkGS4NZcB1QZR5cwJvr94Q+96MBzv45+TtxETw/ER/LApaioH0zNz2CpxWO4fkxxifhYZRmWooOTxasFf0bbyjywRqhoqnX7ikdBimemmfo/0EN8LgO6ld+IIgZ1SbHP2VmrY5h9qqeOPfDJgOtSV5m3GY5aAe9sRaU/4= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=tthayer@opensource.altera.com; Received: from localhost.localdomain (64.129.157.38) by BY1PR03MB1484.namprd03.prod.outlook.com (10.162.210.142) with Microsoft SMTP Server (TLS) id 15.1.390.13; Wed, 27 Jan 2016 16:09:47 +0000 From: To: , , , , , , , , , , Subject: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support Date: Wed, 27 Jan 2016 10:13:20 -0600 Message-ID: <1453911203-30202-1-git-send-email-tthayer@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: CY1PR20CA0112.namprd20.prod.outlook.com (25.164.213.166) To BY1PR03MB1484.namprd03.prod.outlook.com (25.162.210.142) X-MS-Office365-Filtering-Correlation-Id: 785dd137-01d7-4f1b-d6f9-08d327344d7a X-Microsoft-Exchange-Diagnostics-untrusted: 1; BY1PR03MB1484; 2:N8Xod0s506tFmKOKBQnqKr6sH7z7zLD1zO1bjSyBbmMVctC+jlZqMe0y54PKYwuDz79UDEFUXznyzVBrr+TgGeI6DSPGoxXMGXS/qgXSEmJmqMMOysPmWHEqdsDiJ+Vj5QX87UUtFJUPyXYZ0bVQXVLbwpnvd/JGLwEWKVxDFnsMBbGbiFch8+T7fyCCumOq; 3:gs76xRiYaUvU/mDdsAtZWuqP9ycaOUuOPhEsgXuRsfIztqoTYTb8oCS/LP5hMemPBCEh5Hu32oIQwLOpSoZ8eh8+67xwFUNeBDrEQRgbR8MvA5r+bKzfO68+IXuPs6EB; 25:ugF3YZQum8Jwb2zbivqk9DSPLqYSEiREpydcQCdJd/aWoDoUYWEMOuqjWWwGyoC81yEwWs+SqzqklYBf0PKiOfbfTA9ixJwDErsJUJCjoyxQDJYZxXYXlwaj6/uRURFIac+ii6ybqZq1wtrPMLS/NrLHc1fDr8Qm+5m2DtAog5CEAyOwcxAWBib8uGwnMkvx8Zdwkhqo8k1tZ8NaP6Q/xT1CZyCuSfVZLtfw0WAmGsuZjnoMmAvKnkAwS/bLBKfV; 20:y5a/6Ce+oxkNLb5iA66nHzu7PtYFiiCKuF6KdDwjy5n/jtIc90oSUXsJR3XP7WYCPyVLyXgfe6XeXk2aRmcGUIfRFyChYYdFI8tTxe/T6QQT3n7pZE1wXa1Hy/3FgxTXk7/qiabqgs2btu06mZkgGE/S7m/Iuag5bTXaJOO16Wo= X-Exchange-Antispam-Report-Test: UriScan:; BCL:0; PCL:0; RULEID:; SRVR:BY1PR03MB1484; UriScan:(80048183373757); UriScan:; BCL:0; PCL:0; RULEID:(3001016); SRVR:CY1PR0301MB1308; UriScan:(80048183373757); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001); SRVR:BY1PR03MB1484; BCL:0; PCL:0; RULEID:; SRVR:BY1PR03MB1484; BCL:0; PCL:0; RULEID:(601004)(2401047)(8121501046)(13017025)(13024025)(13018025)(5005006)(13015025)(13023025)(3002001)(10201501046); SRVR:CY1PR0301MB1308; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1308; X-Microsoft-Exchange-Diagnostics-untrusted: 1; BY1PR03MB1484; 4:pwzxUxtyNfc6K1FXUtkanEt9yRctOJKWNacZpdiELt81bgY4kO5lGvY7uEKZGzrgxt3ibOqS5EM6ipWKaIln7kNE3IcIC7/lc6s7iMbsMC+wtZvCI07cLEd7Qjjk7lQRO25dYRciQmxENZGtd5AGAKdNHfK4HKKGozSKt7jpnlhPIbmfPDNUw22TAmwd4JIPvCDLS8h3tON6S1u7j9uYD89RsfpYcacRTkMxiaiHW7Bcui7UBmgnZqNT7rn2TRtBzUycRFpfzbMHZXvD/AU7s/vncNQAzBVYAz06sHDxuvxUnJMu0Vt9LeQk6e/ylssoqd5dn82iSq004n4x1tAm2bqEtPAZVpvA5GcGTJxXpcijlP3IgVlNuEZGV4FAjBr7U6M+EtaAXiYBtkfzTrvCp0OqVtlJb6r9MSmosOHE/to= X-Forefront-PRVS: 0834BAF534 X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(6069001)(6009001)(199003)(189002)(2201001)(50226001)(86152002)(105586002)(47776003)(66066001)(33646002)(48376002)(87976001)(50466002)(106356001)(4001430100002)(5001770100001)(5003940100001)(3470700001)(229853001)(5008740100001)(81156007)(4326007)(19580395003)(19580405001)(2876002)(97736004)(50986999)(1096002)(101416001)(86362001)(5001960100002)(77096005)(122386002)(6116002)(586003)(107886002)(3846002)(2906002)(40100003)(92566002)(42186005)(5004730100002)(189998001)(921003)(2004002)(1121003)(217873001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR03MB1484; H:localhost.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; A:0; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: opensource.altera.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics-untrusted: =?us-ascii?Q?1; BY1PR03MB1484; 23:9G5i8vmvljfx36WFSiF6hGmT7AgYjxwVQUAGuYRvM?= =?us-ascii?Q?jBtlt/xizg81k680odHTlvE5MTJ54jngq47ZiTzT0hAA/zDHKY5HodGdfJzp?= =?us-ascii?Q?VusKT+G9r6Z860WUb8GGM65DSp1jP87K36ry/EdXYGAOkimeHMLOwxJcCAQM?= =?us-ascii?Q?S+o29gNj+ZLtXhEUDwBsUqOwuyHSRd9Q6pOriV7kl2aoOaWefID/6hB+l9Po?= =?us-ascii?Q?QsnU41i3xO4bdMS7WY408MWwSBBfN7yU8NvwfUrEiJlkGnmynvjGr0Pm0RX/?= =?us-ascii?Q?ei/fV68B8QbGa8aAbn4f3V8FgrtFkzI+0sDiJgi5/4oKh3NankJxYBJdb6+e?= =?us-ascii?Q?OouWKz7KsaFbDV4oc5DQOXCuLRGaGBFxd6GQ5vNRuZgOyyleraJYRrDIZZlO?= =?us-ascii?Q?L3gWwCIws0b0GI7KLqu/zWey7Z/pZY5VljLkudyFfhHaDR38LsO22yoU1jjd?= =?us-ascii?Q?FGi5HDv5ASM156B/kp49gcJ9oZ9V7mC0ZVIpfMCJ2BbSNlO8LDmdmhEDh6rx?= =?us-ascii?Q?bJBaNzp8Pf2zijWh38RgIZy5p+KUwUSCTW7XEpcC0IAqZ4dthZZbViiZOdB/?= =?us-ascii?Q?CaHdEwoBdksY1b3jdwUaauZn2PUULcQ4FqweDk7XUwXdmMgZ2QDUlXVMr8XM?= =?us-ascii?Q?Vp6FIVI9/TixEJOuHhPHvRXfxcc6vfwMv+nNnXDor3VXRZTnPEen2bELuvvW?= =?us-ascii?Q?Xloh323ebisFcEKugvOIef80nhHNB7LWHPRs2iUu1jy+L/UwJvzrgj6DYoYL?= =?us-ascii?Q?VHHnlq03Va/24ZLjmSdSP1BF8UY/MI+ahrqpFbgemEr5FDsm03nhxqG5/ImQ?= =?us-ascii?Q?QIXJ4+lzaFyZb50ey7t1JE+QnJCPVocS3aAwXOLGNHNTeZs2/UtwSK8vkd56?= =?us-ascii?Q?ASi5AqUPYklq7ZNWXBRiJj94dl11BX4fzFfIudVIOvhnQqH/Kk+GIwOTWb2+?= =?us-ascii?Q?bdG4yB8Wmht8ob+TkWj1NX47hq3o9gct8J/pRGE0BxLh2vk/mVX3gS+bZCpM?= =?us-ascii?Q?/PM00rib9v7mEjSOkMpZobXB5ADdzb4G4YKSi2dta787C7Jj+sr1S5705HOu?= =?us-ascii?Q?yiS475r3+O0trNH7V2pnvRBSEoTtJep+ZGCm86K8N6tNhmFOomGlDKXyAOb1?= =?us-ascii?Q?PtF9DHFmQf8uCc/tPJt9hr7FdILidNGux2+TNL1T7hgLs6XEQV9/DiJ44plz?= =?us-ascii?Q?UqmQHSqR5eFGeOVfQVPgxp69hsVJzQpC0fb/sNVNMIjJTX5B9ippF96Hw=3D?= =?us-ascii?Q?=3D?= X-Microsoft-Exchange-Diagnostics-untrusted: 1; BY1PR03MB1484; 5:rOrDW+qOxkdg8K769ajCKDUpn/UJFvFQXwrpfCyCTThbf33fMsOW57xuIBSgTmMsdqXJ8n/KhXi5j6riIurHEeYqjIgK+LEWdt0t8iIx8Z6VFQZzk1LXICwscqn70cvhTMtIhHgoLa+kjfEReEuH4g==; 24:B2RUIAGEx5JCZGjcIVUajPE0O/6Ei2pHZKzC1heaRJnDLv5BILUx6289FnE87EAJgBdpema5IqedjeW6YP7rbguH2JLtVk6PBK+n8TbE25Q=; 20:cGNGjEOkhJXrvLPXMFaFE1JtJ/WNy3cT2yLviuilKG9sEocMVsxPxGFB07g1zw0C//Nq0wB3U4PqBaDFcJAVQ29YN1Tkv89l65mH8V8bzHD52iO6oqn5uzwsAsnocoHMXCdDC8Lv6R79c8VkJwHTbaFaubbU16/jKpyH095qHrI= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1484 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: BN1BFFO11FD005.protection.gbl X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD005; 1:pIX7kws6gmwwNOLuu+U6KaCBDlrz28Va+N6tl2Hae7kdsTsnLkhSpjuy47XYFn3M8GPyI6Y/Jqk4Aw0yVjRk+GJRel4ychdDbcBXX8QQpem7YVcjKxF+5kXNxsfbWLLvoUwSXK/534MPDPRkcj9ccjv9Tnzw8RGbd63UB9e/vPyAJE6b+FMGyMA791gXQt6Lp2qB4R+y/A5PV94XDGHYQq3DlsX5ywREV9vRR7N39G9KPuFMGBntbrYH2iwl2QmxAryZZeoUgUxM2uAjXlIoGVkMBlqv4N/alZDjmJ/Hr/5qYB92l2EjeuF3vCa0oWCZUKldRAV7zCHtMutfGznf9OcwPNL+grcuZkUaWK/MD6WcakyF6REx5itH9lehBm9PGG8/P3D5Pt31H+RNkDF/e8eVP9jWiAdfkKtPUauAKAy8gt6bwX+gYl3ViU8D7LnB X-Forefront-Antispam-Report: CIP:66.35.236.236; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(87936001)(5001960100002)(106466001)(4001430100002)(3846002)(1220700001)(1096002)(107886002)(49486002)(229853001)(5001770100001)(6116002)(105606002)(50986999)(6806005)(97736004)(586003)(6070500001)(956001)(5008740100001)(3470700001)(81156007)(189998001)(19580395003)(66066001)(47776003)(19580405001)(2906002)(122386002)(4326007)(2201001)(50466002)(50226001)(5003940100001)(77096005)(16796002)(86152002)(33646002)(40100003)(85426001)(5004730100002)(48376002)(86362001)(92566002)(2876002)(7099028)(921003)(2004002)(217873001)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR0301MB1308; H:sj-itexedge04.altera.priv.altera.com; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1308; 2:lhhvlQ7LSDC+3LAAXefcYzIgNPr5t9gT7FhS7uVv1Uh4HxNt6xHlKMhji9JWsRJxRe/5z9OljeqMa9XPhjUpArGdqmL2XzZApd7ma83ncuDObpCUWWdqoS5Uu127zTRKNhzwD1l14rIK1o1DcA6T78nyeEFBrgVCrMTIEl7vTA3BFibmgdReS8JbQF8EDrgU; 3:OksbEp++xnGG+DXciDyH2sYptaAGRQdf9n5/xNZHkzSjx1TxNbC6nRlpWdYS8Eq0kwGkJeJDiCfIRjTCY2uMscxYhwloWYSes2niy/qAtm4VEBaLUjHWsqHtpgxQKfSDzWM8emy9sxzw0YqC+WxLGc9f150p6EZ3YI12nDlOl4VyThBnwjDbrgqAwAWf42nKlX4QI4eg1ZAYFZ8b2de78885g6uho2mRzOutdpGX/v/vHh2aQ3FEwzLiE7xmTwLP; 25:G4abMfoidRBXShueoH/qB3hK6s2Ru/6MltaDRKbEvZdPDuPeNKrI+BVjPRa6HQLkVM3z4Zl3fnAsjrDMP5NTSQVEGtPMAjqGSMAih/mBOThj+67ME5l62oo0kRfmwo7YJv4RtryJiSZbDqXxVT5L/mRn9thu2SPkPryTPwAnQ1KOH/3K5Xt3EnK20NSC2efZjbBzFKvCi7TvOCkxkx3mQBbglNeBZ6D7ks4g7nStylw5P2KHxSSI5QG6MLaxaYz2; 20:IgssSrQdDzpw3Xct/QDcqVTjF2BpkttUqVbiKPYVFdxx5RWarxS0MYt233nJpEz+nt0bK6xDBmScrZbDYV1QYz/WdaL+L+QK5bxfd9eTG5XP93iuhsHtXZBuX353aicoFGvEm+hJut/WdLBpIXu8134FmlrYWEnJSTe7zxnvJx4= X-DkimResult-Test: Passed X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1308; 4:fppbwO+ZrDfixEh3xurr+E1UlslStknxbBlTcZMXOZvolFd+rf64VaQIV6mt3SfIGkjrlLtChWMqgAihWl18Lt8s7fjmGVqqIesQtnYbM5K6aCbchWxTWBGEhLtOLp9zp1qTahDI/7lUAN+uyFpw07rWL+bbDEqcGdwFqQeC/qooqfAGWjZn8l4I9sm4obm1i7Q6v/KlrXSVFL+pHhvR3CRjMgb98o94A4biczDSfjN5FylU4WXuVj3UqC7rMu/tb8Zb7CTPGMwr7qPC+f5lA7xdjEJtO9TnJJ8uQAnA2IXym90XZE79af8F4OCwuY1wVSURTatP3Zrojrq+xS0jLUjw1lEPKQ/F/ssvwBlL+c05YJwjL+6ThbK3Kbov/cQRrZefFs12oqFTrgLpAnhGxGnZadNJ/+ExzzEm0F/0RtW7ARpdPgsUfX/Ehoi0YfiTLcQEwBQQiKKZ0Qi5Jkjgp8GbZA2ULwhR0LUzspIqj9cTqfNO3mk6A20nlkwhET5u X-Forefront-PRVS: 0834BAF534 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR0301MB1308; 23:GCm/0yaq0FbS+Ob6btpTWsfhc0YxgqLnlWYWqLm?= =?us-ascii?Q?EJd5rur6brKzP8vl4h+DVfCN496TyKIIyyteGRLxfRsOGX4A0RF0inE1jRuk?= =?us-ascii?Q?0ZsK4HMb4Rkyd4reGaXuvMW5n6MToTSPJdgXw1nR/tqlgZjWDU7tfXHoMZwG?= =?us-ascii?Q?aiFEsgRNmIzfcsuIsTCrnPx8biIcDDGFiCUR6YCP5sVo8y9MuMkXx9fisF4U?= =?us-ascii?Q?NZKeWhLDYKMnp57JiA46FF7fMMufLIV1CR4tML+tr4zlDGpU/y0grfEaIqMX?= =?us-ascii?Q?p/D+Kw4eTMX0u5CVMRniNbBdAfSg/P6hgJtvoAxV5Gv3Io3KSAcs9tOasakt?= =?us-ascii?Q?90LqZmmURJjSghLN9cBstpHIz0ukdZIM1NUumEYwAXf4xWABztxq2rQ4XnYR?= =?us-ascii?Q?klKrEkN3Fj8/bpjmIIxU+PYCCCgxQeZZTiR4d0yY0YUBvWW8fmL3TDhfVvlk?= =?us-ascii?Q?648lcUS/qm3710Zt8oLpNipCvETOo0CkJ7C6jf58VJ4/gEG7ov6YmVKxCWRk?= =?us-ascii?Q?TacwIVIz2xBG2uOjs6vS0hTV5DrALoc2SdG/xvFKmEXg+End8lIBT0XGJ7qt?= =?us-ascii?Q?yyUI/WAA8j05lkSaUVVjpp+BlfNqJAnEH5CdAyfMofBBLfI+4d1Qir81KEL0?= =?us-ascii?Q?vHrRiBo5r3h/64FCDAnAUI00lBKPQAPUkkCkQ+9mgQAEswc/BecoGH2XTQru?= =?us-ascii?Q?CMsABvmOFpw6nshrGJFBLqux7b1w0u3O6IIy/Dl/ZGbBC2KXcS2HQvAAf/oC?= =?us-ascii?Q?065gxS4eivz3PGRKaFBggjJ3eTlB8xMKhYjB1pf+Q363/SVjnOLNdQBl9u6K?= =?us-ascii?Q?slNxAmY2dTrvnk2JTXQjXtm0u+VZbIIm3bRux9e/rbkUvbmkmajam8ne8fnv?= =?us-ascii?Q?EWN29hPRci8TWmncM/jv+D66ncPBjvCQo1mgTczP2bu4RTtQDq7rJFl99NtM?= =?us-ascii?Q?cdIjWD0uq//bx0LwtJd0nwWrg/xNV2AWRCzPeU0/PKRmP4osKoCtUfnbgprb?= =?us-ascii?Q?2yZ+DXnfl+682WNYm0MAcbmhDclbGdawXXTq9s0IL3b1grEU8JcD6YLFUmbI?= =?us-ascii?Q?a+HScoaMWXJbPzn+tJgpbmsSzrk7DmxcMJEZrTd7gQaP5hX0XjJUUShKbw6v?= =?us-ascii?Q?jlkIb53BTEqVZ0p/nrGkqDA3938Oz2QSli1IFzy1cgaaDXQI/LoH8edh4b4D?= =?us-ascii?Q?Q9ewWj//vhbRqkzy+J+Kxi/GCInWSUhK0IDc/eumZ00blSXcq/nZika3Hblo?= =?us-ascii?Q?PS3DHNcNy9INBT9JcIjT6ttZUhgNp9hKttJoxdcB8uX4aDL48dcILWxpDgOZ?= =?us-ascii?Q?CojoQZ3jzm1Ex5dktHVcVFZZmEQIj+Tqxli0AW9sVl62tXfzu4s6tnZWQZyZ?= =?us-ascii?Q?KcXEx7Pw4b7oGoKNenAU3rIxT6QpVVD7erOUjvO/RYpYpUaEvh8d74y5e7UX?= =?us-ascii?Q?pel9iFQnCbw=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1308; 5:Xc8wlycrd9mfwbEBshDpVH54CArQux1Fn/cPnhgdWEU/UkZHC65jvpwpyq3j3fuV+7+ct2LOp2Ad8ur7WItSjYqjC9EO7SWtOYGL6z2cEZwtJPYkTh3Y8A4Y5V3bOrfQxmHvLczCfV/PJR0XHsr49Q==; 24:YiA6s+Uerz4NdK8NhkdtVJCM8AH7hwy06BvF9HNCPmeAF2BT3HKqYIcXtK7SZXWkO4ix09floR2P8EiN3kFIOxMYDahaG02HJkfODjDdR10=; 20:eg3nEK9qohp5WP/9wJWSwN10ShhiqXE+UgKpxMRx0ExK9cMcO23AQckiTIycdPAEL0kkfRaePfPwcE4CLHJo7cqGM7afaYMOmCKy3UGlqNzwdHHWZzCQ2lJzesXO/7EVtekfZeKjD8KBr2w/JqnYC34x6vTJueyDhi2UdFWIw8I= X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2016 16:09:57.7462 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a; Ip=[66.35.236.236]; Helo=[sj-itexedge04.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1308 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160127_081023_481650_835F5C69 X-CRM114-Status: UNSURE ( 5.56 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tthayer.linux@gmail.com, tthayer@opensource.altera.com, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer --- v9: Improve device tree node release. Free managed resources on error path. Fix ocram memory leak. v8: Remove MASK from single bit mask names. s/altr,edac/altr,socfpga-ecc-manager Use debugfs instead of sysfs. Add chip family name to match string. Fix header year. Fix build dependencies & change commit accordingly. s/CONFIG_EDAC_ALTERA_MC/CONFIG_EDAC_ALTERA v7: s/of_get_named_gen_pool/of_gen_pool_get Remove #ifdef for EDAC_DEBUG Use -ENODEV instead of EPROBE_DEFER v6: Convert to nested EDAC in device tree. Force L2 cache on for L2Cache ECC & remove L2 cache syscon for checking enable bit. Update year in header. v5: No change. v4: Change mask defines to use BIT(). Fix comment style to agree with kernel coding style. Better printk description for read != write in trigger. Remove SysFS debugging message. Better dci->mod_name Move gen_pool pointer assignment to end of function. Invert logic to reduce indent in ocram depenency check. Change from dev_err() to edac_printk() Replace magic numbers with defines & comments. Improve error injection test. Change Makefile intermediary name to altr (from alt) v3: Move OCRAM and L2 cache EDAC functions into altera_edac.c instead of separate files. v2: Fix L2 dependency comments. --- drivers/edac/Kconfig | 26 ++- drivers/edac/Makefile | 2 +- drivers/edac/altera_edac.c | 487 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 507 insertions(+), 8 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index ef25000..15a6df4 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -367,14 +367,30 @@ config EDAC_OCTEON_PCI Support for error detection and correction on the Cavium Octeon family of SOCs. -config EDAC_ALTERA_MC - bool "Altera SDRAM Memory Controller EDAC" +config EDAC_ALTERA + bool "Altera SOCFPGA ECC" depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA help Support for error detection and correction on the - Altera SDRAM memory controller. Note that the - preloader must initialize the SDRAM before loading - the kernel. + Altera SOCs. This must be selected for SDRAM ECC. + Note that the preloader must initialize the SDRAM + before loading the kernel. + +config EDAC_ALTERA_L2C + bool "Altera L2 Cache ECC" + depends on EDAC_ALTERA=y + select CACHE_L2X0 + help + Support for error detection and correction on the + Altera L2 cache Memory for Altera SoCs. This option + requires L2 cache so it will force that selection. + +config EDAC_ALTERA_OCRAM + bool "Altera On-Chip RAM ECC" + depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR + help + Support for error detection and correction on the + Altera On-Chip RAM Memory for Altera SoCs. config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index be163e2..f9e4a3e 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -67,6 +67,6 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o -obj-$(CONFIG_EDAC_ALTERA_MC) += altera_edac.o +obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 9296409..07c13a7 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1,5 +1,5 @@ /* - * Copyright Altera Corporation (C) 2014-2015. All rights reserved. + * Copyright Altera Corporation (C) 2014-2016. All rights reserved. * Copyright 2011-2012 Calxeda, Inc. * * This program is free software; you can redistribute it and/or modify it @@ -17,8 +17,10 @@ * Adapted from the highbank_mc_edac driver. */ +#include #include #include +#include #include #include #include @@ -34,6 +36,7 @@ #define EDAC_MOD_STR "altera_edac" #define EDAC_VERSION "1" +#define EDAC_DEVICE "Altera" static const struct altr_sdram_prv_data c5_data = { .ecc_ctrl_offset = CV_CTLCFG_OFST, @@ -75,6 +78,31 @@ static const struct altr_sdram_prv_data a10_data = { .ue_set_mask = A10_DIAGINT_TDERRA_MASK, }; +/************************** EDAC Device Defines **************************/ + +/* OCRAM ECC Management Group Defines */ +#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04 +#define ALTR_OCR_ECC_EN BIT(0) +#define ALTR_OCR_ECC_INJS BIT(1) +#define ALTR_OCR_ECC_INJD BIT(2) +#define ALTR_OCR_ECC_SERR BIT(3) +#define ALTR_OCR_ECC_DERR BIT(4) + +/* L2 ECC Management Group Defines */ +#define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00 +#define ALTR_L2_ECC_EN BIT(0) +#define ALTR_L2_ECC_INJS BIT(1) +#define ALTR_L2_ECC_INJD BIT(2) + +#define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */ +#define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */ +#define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */ +#define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */ + +/*********************** EDAC Memory Controller Functions ****************/ + +/* The SDRAM controller uses the EDAC Memory Controller framework. */ + static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) { struct mem_ctl_info *mci = dev_id; @@ -504,6 +532,461 @@ static struct platform_driver altr_sdram_edac_driver = { module_platform_driver(altr_sdram_edac_driver); +/************************* EDAC Parent Probe *************************/ + +static const struct of_device_id altr_edac_device_of_match[]; + +static const struct of_device_id altr_edac_of_match[] = { + { .compatible = "altr,socfpga-ecc-manager" }, + {}, +}; +MODULE_DEVICE_TABLE(of, altr_edac_of_match); + +static int altr_edac_probe(struct platform_device *pdev) +{ + of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, + NULL, &pdev->dev); + return 0; +} + +static struct platform_driver altr_edac_driver = { + .probe = altr_edac_probe, + .driver = { + .name = "socfpga_ecc_manager", + .of_match_table = altr_edac_of_match, + }, +}; +module_platform_driver(altr_edac_driver); + +/************************* EDAC Device Functions *************************/ + +/* + * EDAC Device Functions (shared between various IPs). + * The discrete memories use the EDAC Device framework. The probe + * and error handling functions are very similar between memories + * so they are shared. The memory allocation and freeing for EDAC + * trigger testing are different for each memory. + */ + +const struct edac_device_prv_data ocramecc_data; +const struct edac_device_prv_data l2ecc_data; + +struct edac_device_prv_data { + int (*setup)(struct platform_device *pdev, void __iomem *base); + int ce_clear_mask; + int ue_clear_mask; + struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr; + char dbgfs_name[20]; + void * (*alloc_mem)(size_t size, void **other); + void (*free_mem)(void *p, size_t size, void *other); + int ecc_enable_mask; + int ce_set_mask; + int ue_set_mask; + int trig_alloc_sz; +}; + +struct altr_edac_device_dev { + void __iomem *base; + int sb_irq; + int db_irq; + const struct edac_device_prv_data *data; + char *edac_dev_name; +}; + +static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) +{ + struct edac_device_ctl_info *dci = dev_id; + struct altr_edac_device_dev *drvdata = dci->pvt_info; + const struct edac_device_prv_data *priv = drvdata->data; + + if (irq == drvdata->sb_irq) { + if (priv->ce_clear_mask) + writel(priv->ce_clear_mask, drvdata->base); + edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); + } + if (irq == drvdata->db_irq) { + if (priv->ue_clear_mask) + writel(priv->ue_clear_mask, drvdata->base); + edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); + panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); + } + + return IRQ_HANDLED; +} + +static ssize_t altr_edac_device_trig(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) + +{ + u32 *ptemp, i, error_mask; + int result = 0; + u8 trig_type; + unsigned long flags; + struct edac_device_ctl_info *edac_dci = file->private_data; + struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; + const struct edac_device_prv_data *priv = drvdata->data; + void *generic_ptr = edac_dci->dev; + + if (!user_buf || get_user(trig_type, user_buf)) + return -EFAULT; + + if (!priv->alloc_mem) + return -ENOMEM; + + /* + * Note that generic_ptr is initialized to the device * but in + * some alloc_functions, this is overridden and returns data. + */ + ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); + if (!ptemp) { + edac_printk(KERN_ERR, EDAC_DEVICE, + "Inject: Buffer Allocation error\n"); + return -ENOMEM; + } + + if (trig_type == ALTR_UE_TRIGGER_CHAR) + error_mask = priv->ue_set_mask; + else + error_mask = priv->ce_set_mask; + + edac_printk(KERN_ALERT, EDAC_DEVICE, + "Trigger Error Mask (0x%X)\n", error_mask); + + local_irq_save(flags); + /* write ECC corrupted data out. */ + for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { + /* Read data so we're in the correct state */ + rmb(); + if (ACCESS_ONCE(ptemp[i])) + result = -1; + /* Toggle Error bit (it is latched), leave ECC enabled */ + writel(error_mask, drvdata->base); + writel(priv->ecc_enable_mask, drvdata->base); + ptemp[i] = i; + } + /* Ensure it has been written out */ + wmb(); + local_irq_restore(flags); + + if (result) + edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); + + /* Read out written data. ECC error caused here */ + for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) + if (ACCESS_ONCE(ptemp[i]) != i) + edac_printk(KERN_ERR, EDAC_DEVICE, + "Read doesn't match written data\n"); + + if (priv->free_mem) + priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); + + return count; +} + +static const struct file_operations altr_edac_device_inject_fops = { + .open = simple_open, + .write = altr_edac_device_trig, + .llseek = generic_file_llseek, +}; + +static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, + const struct edac_device_prv_data *priv, + struct dentry *debugfs) +{ + if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) + return; + + edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR, + debugfs, edac_dci, + &altr_edac_device_inject_fops); +} + +static const struct of_device_id altr_edac_device_of_match[] = { +#ifdef CONFIG_EDAC_ALTERA_L2C + { .compatible = "altr,socfpga-l2-ecc", .data = (void *)&l2ecc_data }, +#endif +#ifdef CONFIG_EDAC_ALTERA_OCRAM + { .compatible = "altr,socfpga-ocram-ecc", + .data = (void *)&ocramecc_data }, +#endif + {}, +}; +MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); + +/* + * altr_edac_device_probe() + * This is a generic EDAC device driver that will support + * various Altera memory devices such as the L2 cache ECC and + * OCRAM ECC as well as the memories for other peripherals. + * Module specific initialization is done by passing the + * function index in the device tree. + */ +static int altr_edac_device_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *dci; + struct altr_edac_device_dev *drvdata; + struct resource *r; + int res = 0; + struct device_node *np = pdev->dev.of_node; + char *ecc_name = (char *)np->name; + static int dev_instance; + struct dentry *debugfs; + + if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { + edac_printk(KERN_ERR, EDAC_DEVICE, + "Unable to open devm\n"); + return -ENOMEM; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + edac_printk(KERN_ERR, EDAC_DEVICE, + "Unable to get mem resource\n"); + res = -ENODEV; + goto fail; + } + + if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), + dev_name(&pdev->dev))) { + edac_printk(KERN_ERR, EDAC_DEVICE, + "%s:Error requesting mem region\n", ecc_name); + res = -EBUSY; + goto fail; + } + + dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, + 1, ecc_name, 1, 0, NULL, 0, + dev_instance++); + + if (!dci) { + edac_printk(KERN_ERR, EDAC_DEVICE, + "%s: Unable to allocate EDAC device\n", ecc_name); + res = -ENOMEM; + goto fail; + } + + drvdata = dci->pvt_info; + dci->dev = &pdev->dev; + platform_set_drvdata(pdev, dci); + drvdata->edac_dev_name = ecc_name; + + drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); + if (!drvdata->base) + goto fail1; + + /* Get driver specific data for this EDAC device */ + drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; + + /* Check specific dependencies for the module */ + if (drvdata->data->setup) { + res = drvdata->data->setup(pdev, drvdata->base); + if (res < 0) + goto fail1; + } + + drvdata->sb_irq = platform_get_irq(pdev, 0); + res = devm_request_irq(&pdev->dev, drvdata->sb_irq, + altr_edac_device_handler, + 0, dev_name(&pdev->dev), dci); + if (res < 0) + goto fail1; + + drvdata->db_irq = platform_get_irq(pdev, 1); + res = devm_request_irq(&pdev->dev, drvdata->db_irq, + altr_edac_device_handler, + 0, dev_name(&pdev->dev), dci); + if (res < 0) + goto fail1; + + dci->mod_name = "Altera ECC Manager"; + dci->dev_name = drvdata->edac_dev_name; + + debugfs = edac_debugfs_create_dir(ecc_name); + if (debugfs) + altr_create_edacdev_dbgfs(dci, drvdata->data, debugfs); + + if (edac_device_add_device(dci)) + goto fail1; + + devres_close_group(&pdev->dev, NULL); + + return 0; + +fail1: + edac_device_free_ctl_info(dci); +fail: + devres_release_group(&pdev->dev, NULL); + edac_printk(KERN_ERR, EDAC_DEVICE, + "%s:Error setting up EDAC device: %d\n", ecc_name, res); + + return res; +} + +static int altr_edac_device_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); + + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(dci); + + return 0; +} + +static struct platform_driver altr_edac_device_driver = { + .probe = altr_edac_device_probe, + .remove = altr_edac_device_remove, + .driver = { + .name = "altr_edac_device", + .of_match_table = altr_edac_device_of_match, + }, +}; +module_platform_driver(altr_edac_device_driver); + +/*********************** OCRAM EDAC Device Functions *********************/ + +#ifdef CONFIG_EDAC_ALTERA_OCRAM + +static void *ocram_alloc_mem(size_t size, void **other) +{ + struct device_node *np; + struct gen_pool *gp; + void *sram_addr; + + np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); + if (!np) + return NULL; + + gp = of_gen_pool_get(np, "iram", 0); + of_node_put(np); + if (!gp) + return NULL; + + sram_addr = (void *)gen_pool_alloc(gp, size); + if (!sram_addr) + return NULL; + + memset(sram_addr, 0, size); + wmb(); /* Ensure data is written out */ + + *other = gp; /* Remember this handle for freeing later */ + + return sram_addr; +} + +static void ocram_free_mem(void *p, size_t size, void *other) +{ + gen_pool_free((struct gen_pool *)other, (u32)p, size); +} + +/* + * altr_ocram_dependencies() + * Test for OCRAM cache ECC dependencies upon entry because + * platform specific startup should have initialized the + * On-Chip RAM memory and enabled the ECC. + * Can't turn on ECC here because accessing un-initialized + * memory will cause CE/UE errors possibly causing an ABORT. + */ +static int altr_ocram_dependencies(struct platform_device *pdev, + void __iomem *base) +{ + u32 control; + + control = readl(base) & ALTR_OCR_ECC_EN; + if (control) + return 0; + + edac_printk(KERN_ERR, EDAC_DEVICE, + "OCRAM: No ECC present or ECC disabled.\n"); + return -ENODEV; +} + +const struct edac_device_prv_data ocramecc_data = { + .setup = altr_ocram_dependencies, + .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), + .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), + .dbgfs_name = "altr_ocram_trigger", + .alloc_mem = ocram_alloc_mem, + .free_mem = ocram_free_mem, + .ecc_enable_mask = ALTR_OCR_ECC_EN, + .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), + .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), + .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, +}; + +#endif /* CONFIG_EDAC_ALTERA_OCRAM */ + +/********************* L2 Cache EDAC Device Functions ********************/ + +#ifdef CONFIG_EDAC_ALTERA_L2C + +static void *l2_alloc_mem(size_t size, void **other) +{ + struct device *dev = *other; + void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); + + if (!ptemp) + return NULL; + + /* Make sure everything is written out */ + wmb(); + + /* + * Clean all cache levels up to LoC (includes L2) + * This ensures the corrupted data is written into + * L2 cache for readback test (which causes ECC error). + */ + flush_cache_all(); + + return ptemp; +} + +static void l2_free_mem(void *p, size_t size, void *other) +{ + struct device *dev = other; + + if (dev && p) + devm_kfree(dev, p); +} + +/* + * altr_l2_dependencies() + * Test for L2 cache ECC dependencies upon entry because + * platform specific startup should have initialized the L2 + * memory and enabled the ECC. + * Bail if ECC is not enabled. + * Note that L2 Cache Enable is forced at build time. + */ +static int altr_l2_dependencies(struct platform_device *pdev, + void __iomem *base) +{ + u32 control; + + control = readl(base) & ALTR_L2_ECC_EN; + if (!control) { + edac_printk(KERN_ERR, EDAC_DEVICE, + "L2: No ECC present, or ECC disabled\n"); + return -ENODEV; + } + + return 0; +} + +const struct edac_device_prv_data l2ecc_data = { + .setup = altr_l2_dependencies, + .ce_clear_mask = 0, + .ue_clear_mask = 0, + .dbgfs_name = "altr_l2_trigger", + .alloc_mem = l2_alloc_mem, + .free_mem = l2_free_mem, + .ecc_enable_mask = ALTR_L2_ECC_EN, + .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), + .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), + .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, +}; + +#endif /* CONFIG_EDAC_ALTERA_L2C */ + MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Thor Thayer"); -MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller"); +MODULE_DESCRIPTION("EDAC Driver for Altera Memories");