From patchwork Sat Jan 30 06:46:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 8169801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8833FBEEE5 for ; Sat, 30 Jan 2016 06:48:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8188C20397 for ; Sat, 30 Jan 2016 06:48:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6BB0C20395 for ; Sat, 30 Jan 2016 06:48:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aPPJD-0004oL-0H; Sat, 30 Jan 2016 06:46:59 +0000 Received: from mail-qg0-x22e.google.com ([2607:f8b0:400d:c04::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aPPJ9-0004mb-27 for linux-arm-kernel@lists.infradead.org; Sat, 30 Jan 2016 06:46:56 +0000 Received: by mail-qg0-x22e.google.com with SMTP id o11so82764223qge.2 for ; Fri, 29 Jan 2016 22:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=YKkULl1Wi1oKCRkAcD3Q/+/zH37gBQqFl4l5ttW6FmI=; b=uh5s0xJthOMUOheflAufHKTcNOZB8WGsu+RrdpESmo/h/t7bn0P0z/DMCzCd452YBR lgSHYDUbboJh1W9YWeYbhQvb8wzoIPTW47Qn44ZbkvYUVPMC85Hj8P8W9wFZsDXj7olP hD63NxHsrC+iTbj4ghcuN8yCm1ALH3ymjAJUrg9d3cEEc10iI+G8+Q9XRFY+zQ+sXGjj E8ea13oGSPqNYUWTAlvAKjtsyXxjQ+4w0tM68yusE7IhyW5ZSyaLtPUt+Tbdln7UaN7M O4Q6o0CH4DO/uM/MM3+2BYp+0SpgGwJW+G0G2m+ub8q4CHs8gdGaQgOfB8eS9ZGzKtIe o34A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=YKkULl1Wi1oKCRkAcD3Q/+/zH37gBQqFl4l5ttW6FmI=; b=JKj7UQSeJME74g6yefB8BmC00csBruveICcQThkAT9fWBKgSBZH+EZe+XmUQFQQ6Kv ECQlhFLU37J2+Pu+/S3KyCyz2Ft4EIc2viDTYI6mA7EEYHchhkMKeRI2qLNQlIcB4Wax LY7p2DD84ORojBLJ4j2kRpg+4s9K5XSCOIx3YjRO7tImao9W/PUnSSzjLC0ogPr3I5SL RsfVuGTenS3mwCWs8MJKopgL6ETAh5WLyQr9olPfAUteoxLmdpr4ZbzW2Q7KplPyqn1T itBKWHggKcK0LqiWISYsRYkgSoPTIt95F52tWlBsbki+e94RPcmj1hb6yiGHjVFf16T9 tKHg== X-Gm-Message-State: AG10YORShEcRA1y3NXit+mGJFtxgx+f6eTrcETsuPj8GFNEPqbd/OZDbAYwGuBaG0yCT3g== X-Received: by 10.140.217.67 with SMTP id n64mr16780313qhb.26.1454136393767; Fri, 29 Jan 2016 22:46:33 -0800 (PST) Received: from localhost.localdomain ([190.2.108.156]) by smtp.gmail.com with ESMTPSA id x136sm7735033qka.0.2016.01.29.22.46.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Jan 2016 22:46:32 -0800 (PST) From: Ezequiel Garcia To: Subject: [PATCH 1/2] clocksource/drivers/lpc32xx: Support periodic mode Date: Sat, 30 Jan 2016 03:46:18 -0300 Message-Id: <1454136379-7517-1-git-send-email-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.7.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160129_224655_326114_9D0542B1 X-CRM114-Status: GOOD ( 16.61 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Gleixner , Daniel Lezcano , Joachim Eastwood , Ezequiel Garcia MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds the support for periodic mode. This is done by not setting the MR0S (Stop on TnMR0) bit on MCR, thus allowing interrupts to be periodically generated on MR0 matches. In order to do this, move the initial configuration that is specific to the one shot mode to clock_event_device.set_state_oneshot. Signed-off-by: Ezequiel Garcia --- drivers/clocksource/time-lpc32xx.c | 48 ++++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/time-lpc32xx.c b/drivers/clocksource/time-lpc32xx.c index 1316876b487a..9b3d4a38c716 100644 --- a/drivers/clocksource/time-lpc32xx.c +++ b/drivers/clocksource/time-lpc32xx.c @@ -47,6 +47,8 @@ struct lpc32xx_clock_event_ddata { /* Needed for the sched clock */ static void __iomem *clocksource_timer_counter; +/* Needed for clockevents periodic mode */ +static u32 ticks_per_jiffy; static u64 notrace lpc32xx_read_sched_clock(void) { @@ -86,11 +88,42 @@ static int lpc32xx_clkevt_shutdown(struct clock_event_device *evtdev) static int lpc32xx_clkevt_oneshot(struct clock_event_device *evtdev) { + struct lpc32xx_clock_event_ddata *ddata = + container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev); + /* * When using oneshot, we must also disable the timer * to wait for the first call to set_next_event(). */ - return lpc32xx_clkevt_shutdown(evtdev); + writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); + + /* Enable interrupt, reset on match and stop on match (MCR). */ + writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | + LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR); + /* Configure a compare match value of 1 on MR0. */ + writel_relaxed(1, ddata->base + LPC32XX_TIMER_MR0); + + return 0; +} + +static int lpc32xx_clkevt_periodic(struct clock_event_device *evtdev) +{ + struct lpc32xx_clock_event_ddata *ddata = + container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev); + + /* Enable interrupt and reset on match. */ + writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R, + ddata->base + LPC32XX_TIMER_MCR); + /* + * Place timer in reset and set a match value on MR0. An interrupt will + * be generated each time the counter matches MR0. After setup the + * timer is released from reset and enabled. + */ + writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); + writel_relaxed(ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); + writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); + + return 0; } static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id) @@ -108,11 +141,14 @@ static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id) static struct lpc32xx_clock_event_ddata lpc32xx_clk_event_ddata = { .evtdev = { .name = "lpc3220 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC, .rating = 300, .set_next_event = lpc32xx_clkevt_next_event, .set_state_shutdown = lpc32xx_clkevt_shutdown, .set_state_oneshot = lpc32xx_clkevt_oneshot, + .set_state_periodic = lpc32xx_clkevt_periodic, + .tick_resume = lpc32xx_clkevt_shutdown, }, }; @@ -210,17 +246,15 @@ static int __init lpc32xx_clockevent_init(struct device_node *np) /* * Disable timer and clear any pending interrupt (IR) on match - * channel 0 (MR0). Configure a compare match value of 1 on MR0 - * and enable interrupt, reset on match and stop on match (MCR). + * channel 0 (MR0). Enable interrupt, reset on match and stop + * on match (MCR). */ writel_relaxed(0, base + LPC32XX_TIMER_TCR); writel_relaxed(0, base + LPC32XX_TIMER_CTCR); writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR); - writel_relaxed(1, base + LPC32XX_TIMER_MR0); - writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | - LPC32XX_TIMER_MCR_MR0S, base + LPC32XX_TIMER_MCR); rate = clk_get_rate(clk); + ticks_per_jiffy = (rate + HZ/2) / HZ; lpc32xx_clk_event_ddata.base = base; clockevents_config_and_register(&lpc32xx_clk_event_ddata.evtdev, rate, 1, -1);