From patchwork Wed Feb 3 04:12:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 8197791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EBF779F38B for ; Wed, 3 Feb 2016 04:16:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EB6F62025B for ; Wed, 3 Feb 2016 04:16:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 00B1320221 for ; Wed, 3 Feb 2016 04:16:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQoqA-0004Ke-Od; Wed, 03 Feb 2016 04:14:50 +0000 Received: from mail-pa0-f68.google.com ([209.85.220.68]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQopW-0003hY-7N; Wed, 03 Feb 2016 04:14:13 +0000 Received: by mail-pa0-f68.google.com with SMTP id y7so387291paa.3; Tue, 02 Feb 2016 20:13:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLNSXzh3XVp37zQQi7vfvsYT+Df2b9xG3GFSyFOO4Ik=; b=JYOWK6a65Fgu1vCPU1Axqp8eviIPAB756rn/5+bSZASct/0vhFYml90umB0k04TYaa FBjTjWuBV1dtgVGwESbN+LtdzEwrzv6aaWtsE26995Fk0+Sn5n3hNRGDxojYOcL666/D mMzBG5IVlAELNUoadA4WZ4/Jng2J/DXfNsKFutkiqpaF11x0VeXug7vp4wV6zQbUKRKd /SVF+oHPWyOAxf23vYgAjoGHhHj4mc3TdwlS2ZpgaQgvlBGNOsTqNME9qLPMgwVZUvXt BfCoiuuDV3fXasBgaWlg/WQvECP3o9kfeUJT6mw9oEZKcqiySeJE7U1Z359QH6ex7UwH Tqjg== X-Gm-Message-State: AG10YORDCPBrbdjStqw+rVvUn1fSv/UjaHAfhJEadMRFDnPqaMeQpPGIcxW8yfDgBkiF9g== X-Received: by 10.66.193.233 with SMTP id hr9mr52842605pac.18.1454472833467; Tue, 02 Feb 2016 20:13:53 -0800 (PST) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id cf6sm5809274pad.41.2016.02.02.20.13.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 Feb 2016 20:13:52 -0800 (PST) From: Caesar Wang To: Heiko Stuebner , edubezval@gmail.com Subject: [PATCH 5/8] thermal: rockchip: the rename compatibles for rockchip SoCs Date: Wed, 3 Feb 2016 12:12:44 +0800 Message-Id: <1454472767-5767-6-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454472767-5767-1-git-send-email-wxt@rock-chips.com> References: <1454472767-5767-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160202_201410_503757_009FD890 X-CRM114-Status: GOOD ( 10.20 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangtao@rock-chips.com, Dmitry Torokhov , linux-pm@vger.kernel.org, zhangqing@rock-chips.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Zhang Rui , linux-arm-kernel@lists.infradead.org, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch renames to be more adapter compatibles since more and more SoCs are supported in thermal driver. Reported-by: Huang,Tao Signed-off-by: Caesar Wang --- drivers/thermal/rockchip_thermal.c | 50 +++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 5c58d48..9cdef62 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -58,8 +58,8 @@ enum sensor_id { /** * The conversion table has the adc value and temperature. - * ADC_DECREMENT: the adc value is of diminishing.(e.g. v2_code_table) - * ADC_INCREMENT: the adc value is incremental.(e.g. v3_code_table) + * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) + * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) */ enum adc_sort_mode { ADC_DECREMENT = 0, @@ -135,7 +135,13 @@ struct rockchip_thermal_data { enum tshut_polarity tshut_polarity; }; -/* TSADC Sensor info define: */ +/** + * TSADC Sensor Register description: + * + * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. + * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) + * + */ #define TSADCV2_AUTO_CON 0x04 #define TSADCV2_INT_EN 0x08 #define TSADCV2_INT_PD 0x0c @@ -154,8 +160,8 @@ struct rockchip_thermal_data { #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) -#define TSADCV1_INT_PD_CLEAR_MASK ~BIT(16) #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) +#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) #define TSADCV2_DATA_MASK 0xfff #define TSADCV3_DATA_MASK 0x3ff @@ -177,7 +183,7 @@ struct tsadc_table { * linearly interpolated. * Code to Temperature mapping should be updated based on sillcon results. */ -static const struct tsadc_table v1_code_table[] = { +static const struct tsadc_table rk3228_code_table[] = { {TSADCV3_DATA_MASK, -40000}, {436, -40000}, {431, -35000}, @@ -215,7 +221,7 @@ static const struct tsadc_table v1_code_table[] = { {264, 125000}, }; -static const struct tsadc_table v2_code_table[] = { +static const struct tsadc_table rk3288_code_table[] = { {TSADCV2_DATA_MASK, -40000}, {3800, -40000}, {3792, -35000}, @@ -253,7 +259,7 @@ static const struct tsadc_table v2_code_table[] = { {3421, 125000}, }; -static const struct tsadc_table v3_code_table[] = { +static const struct tsadc_table rk3368_code_table[] = { {0, -40000}, {106, -40000}, {108, -35000}, @@ -292,7 +298,7 @@ static const struct tsadc_table v3_code_table[] = { {TSADCV3_DATA_MASK, 125000}, }; -static const struct tsadc_table v4_code_table[] = { +static const struct tsadc_table rk3399_code_table[] = { {TSADCV3_DATA_MASK, -40000}, {431, -40000}, {426, -35000}, @@ -453,20 +459,20 @@ static void rk_tsadcv2_initialize(void __iomem *regs, regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); } -static void rk_tsadcv1_irq_ack(void __iomem *regs) +static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; val = readl_relaxed(regs + TSADCV2_INT_PD); - writel_relaxed(val & TSADCV1_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); + writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); } -static void rk_tsadcv2_irq_ack(void __iomem *regs) +static void rk_tsadcv3_irq_ack(void __iomem *regs) { u32 val; val = readl_relaxed(regs + TSADCV2_INT_PD); - writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); + writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); } static void rk_tsadcv2_control(void __iomem *regs, bool enable) @@ -531,15 +537,15 @@ static const struct rockchip_tsadc_chip rk3228_tsadc_data = { .tshut_temp = 95000, .initialize = rk_tsadcv2_initialize, - .irq_ack = rk_tsadcv1_irq_ack, + .irq_ack = rk_tsadcv3_irq_ack, .control = rk_tsadcv2_control, .get_temp = rk_tsadcv2_get_temp, .set_tshut_temp = rk_tsadcv2_tshut_temp, .set_tshut_mode = rk_tsadcv2_tshut_mode, .table = { - .id = v1_code_table, - .length = ARRAY_SIZE(v1_code_table), + .id = rk3228_code_table, + .length = ARRAY_SIZE(rk3228_code_table), .data_mask = TSADCV3_DATA_MASK, .mode = ADC_DECREMENT, }, @@ -562,8 +568,8 @@ static const struct rockchip_tsadc_chip rk3288_tsadc_data = { .set_tshut_mode = rk_tsadcv2_tshut_mode, .table = { - .id = v2_code_table, - .length = ARRAY_SIZE(v2_code_table), + .id = rk3288_code_table, + .length = ARRAY_SIZE(rk3288_code_table), .data_mask = TSADCV2_DATA_MASK, .mode = ADC_DECREMENT, }, @@ -586,8 +592,8 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_data = { .set_tshut_mode = rk_tsadcv2_tshut_mode, .table = { - .id = v3_code_table, - .length = ARRAY_SIZE(v3_code_table), + .id = rk3368_code_table, + .length = ARRAY_SIZE(rk3368_code_table), .data_mask = TSADCV3_DATA_MASK, .mode = ADC_INCREMENT, }, @@ -603,15 +609,15 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = { .tshut_temp = 95000, .initialize = rk_tsadcv2_initialize, - .irq_ack = rk_tsadcv1_irq_ack, + .irq_ack = rk_tsadcv3_irq_ack, .control = rk_tsadcv2_control, .get_temp = rk_tsadcv2_get_temp, .set_tshut_temp = rk_tsadcv2_tshut_temp, .set_tshut_mode = rk_tsadcv2_tshut_mode, .table = { - .id = v4_code_table, - .length = ARRAY_SIZE(v4_code_table), + .id = rk3399_code_table, + .length = ARRAY_SIZE(rk3399_code_table), .data_mask = TSADCV3_DATA_MASK, .mode = ADC_DECREMENT, },