From patchwork Wed Feb 3 11:30:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 8200931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9924D9F3CD for ; Wed, 3 Feb 2016 11:34:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D88AA2035E for ; Wed, 3 Feb 2016 11:34:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FE182034E for ; Wed, 3 Feb 2016 11:34:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQvgN-00032L-Ew; Wed, 03 Feb 2016 11:33:11 +0000 Received: from mailapp01.imgtec.com ([195.59.15.196]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQvgI-0002sa-OQ for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2016 11:33:08 +0000 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id 3E880BFD97783; Wed, 3 Feb 2016 11:32:48 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 3 Feb 2016 11:32:49 +0000 Received: from localhost (10.100.200.105) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 3 Feb 2016 11:32:49 +0000 From: Paul Burton To: , Ralf Baechle Subject: [PATCH v2 07/15] PCI: xilinx: Clear interrupt FIFO during probe Date: Wed, 3 Feb 2016 11:30:37 +0000 Message-ID: <1454499045-5020-8-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.105] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160203_033307_143577_403D8161 X-CRM114-Status: UNSURE ( 8.48 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , linux-kernel@vger.kernel.org, Paul Burton , linux-pci@vger.kernel.org, Michal Simek , Russell Joyce , Grygorii Strashko , linux-arm-kernel@lists.infradead.org, Jingoo Han , Bjorn Helgaas , Thomas Gleixner , Jiang Liu , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP xilinx_pcie_init_port clears the pending interrupts in the interrupt decode register, but does not clear the interrupt FIFO. This would lead to spurious interrupts if any were present in the FIFO at probe time. Clear the interrupt FIFO prior to the interrupt decode register in order to start with a clean slate as expected. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 1eb74a2..6c5a503 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -568,6 +568,8 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) */ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) { + u32 val; + if (xilinx_pcie_link_is_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); else @@ -577,6 +579,17 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK, XILINX_PCIE_REG_IMR); + /* Clear interrupt FIFO */ + while (1) { + val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + + if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) + break; + + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); + } + /* Clear pending interrupts */ pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) & XILINX_PCIE_IMR_ALL_MASK,