From patchwork Wed Feb 3 23:33:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Adamski X-Patchwork-Id: 8212071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3948ABEEE5 for ; Wed, 3 Feb 2016 23:37:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 63C92202F0 for ; Wed, 3 Feb 2016 23:37:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8462A202BE for ; Wed, 3 Feb 2016 23:37:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aR6xg-0007Da-4H; Wed, 03 Feb 2016 23:35:48 +0000 Received: from box2.japko.eu ([91.121.152.53]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aR6wn-00053j-KH for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2016 23:34:55 +0000 Received: by box2.japko.eu (Postfix, from userid 1000) id 52C6C6285E; Thu, 4 Feb 2016 00:34:04 +0100 (CET) From: Krzysztof Adamski To: inus Walleij , Maxime Ripard , Chen-Yu Tsai , Hans de Goede , Lee Jones , Rob Herring , Jens Kuske , Fabian Frederick , Vishnu Patekar , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v3 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Date: Thu, 4 Feb 2016 00:33:50 +0100 Message-Id: <1454542430-16572-6-git-send-email-k@japko.eu> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454542430-16572-1-git-send-email-k@japko.eu> References: <1454542430-16572-1-git-send-email-k@japko.eu> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160203_153454_218932_D143DB83 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Adamski MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP sunxi_pmx_set accepts pin number and then calculates offset by subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, gets offset so we have to convert it to pin number so we won't get negative value in sunxi_pmx_set. This was only used on A10 so far, where there is only one GPIO chip with pin_base set to 0 so it didn't matter. However H3 also requires this workaround but have two pinmux sections, triggering problem for PL port. Signed-off-by: Krzysztof Adamski Acked-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 7a2465f..96f64a1 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -459,15 +459,16 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) u8 index = sunxi_data_offset(offset); u32 set_mux = pctl->desc->irq_read_needs_mux && test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags); + u32 pin = offset + chip->base; u32 val; if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT); + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ); + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); return !!val; }