diff mbox

[V2,03/12] dtb: amd: Fix DMA ranges in device tree

Message ID 1454954357-8395-4-git-send-email-Suravee.Suthikulpanit@amd.com (mailing list archive)
State New, archived
Headers show

Commit Message

Suravee Suthikulpanit Feb. 8, 2016, 5:59 p.m. UTC 
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

Comments

Arnd Bergmann Feb. 9, 2016, 2:57 p.m. UTC | #1 
On Monday 08 February 2016 11:59:08 Suravee Suthikulpanit wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> 
> Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.
> 
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> 

This could use a changelog text to explain why it's broken and how the
fix works.

	Arnd
Suravee Suthikulpanit Feb. 10, 2016, 9:13 p.m. UTC | #2 
Hi Arnd,

On 2/9/16 21:57, Arnd Bergmann wrote:
> On Monday 08 February 2016 11:59:08 Suravee Suthikulpanit wrote:
>> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>
>> Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.
>>
>> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>
>
> This could use a changelog text to explain why it's broken and how the
> fix works.
>
> 	Arnd
>

So, I have not experience the breakage. However, IIUC, the GICv2m MSI 
frame is also considered DMA-able. So, I think it should be included in 
the dma-range specified here. Please let me know if my assumption is 
incorrect. Otherwise, I will include more description in the commit log 
in my next rev.

Thanks,
Suravee
Arnd Bergmann Feb. 10, 2016, 9:19 p.m. UTC | #3 
On Thursday 11 February 2016 04:13:50 Suravee Suthikulpanit wrote:
> 
> On 2/9/16 21:57, Arnd Bergmann wrote:
> > On Monday 08 February 2016 11:59:08 Suravee Suthikulpanit wrote:
> >> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> >>
> >> Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.
> >>
> >> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> >>
> >
> > This could use a changelog text to explain why it's broken and how the
> > fix works.
> >
> >       Arnd
> >
> 
> So, I have not experience the breakage. However, IIUC, the GICv2m MSI 
> frame is also considered DMA-able. So, I think it should be included in 
> the dma-range specified here. Please let me know if my assumption is 
> incorrect. Otherwise, I will include more description in the commit log 
> in my next rev.

No, I think this makes sense. Just put a more explanation into the changelog
when those things are not obvious from looking at the change.

	Arnd
Olof Johansson Feb. 11, 2016, 9:23 p.m. UTC | #4 
Hi,

On Wed, Feb 10, 2016 at 1:13 PM, Suravee Suthikulpanit
<Suravee.Suthikulpanit@amd.com> wrote:
> Hi Arnd,
>
>
> On 2/9/16 21:57, Arnd Bergmann wrote:
>>
>> On Monday 08 February 2016 11:59:08 Suravee Suthikulpanit wrote:
>>>
>>> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>>
>>> Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.
>>>
>>> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>>
>>
>> This could use a changelog text to explain why it's broken and how the
>> fix works.
>>
>>         Arnd
>>
>
> So, I have not experience the breakage. However, IIUC, the GICv2m MSI frame
> is also considered DMA-able. So, I think it should be included in the
> dma-range specified here. Please let me know if my assumption is incorrect.
> Otherwise, I will include more description in the commit log in my next rev.

As I replied when I did it -- I've applied the patches, so respinning
won't work. Instead, please follow up with incremental fixes to this
series instead.


Thanks,

-Olof
Suravee Suthikulpanit Feb. 11, 2016, 10:59 p.m. UTC | #5 
Ok, I'll send the incremental patch out again.

Thanks,
Suravee

On 2/12/16 04:23, Olof Johansson wrote:
> Hi,
>
> On Wed, Feb 10, 2016 at 1:13 PM, Suravee Suthikulpanit
> <Suravee.Suthikulpanit@amd.com> wrote:
>> Hi Arnd,
>>
>>
>> On 2/9/16 21:57, Arnd Bergmann wrote:
>>>
>>> On Monday 08 February 2016 11:59:08 Suravee Suthikulpanit wrote:
>>>>
>>>> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>>>
>>>> Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.
>>>>
>>>> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>>>
>>>
>>> This could use a changelog text to explain why it's broken and how the
>>> fix works.
>>>
>>>          Arnd
>>>
>>
>> So, I have not experience the breakage. However, IIUC, the GICv2m MSI frame
>> is also considered DMA-able. So, I think it should be included in the
>> dma-range specified here. Please let me know if my assumption is incorrect.
>> Otherwise, I will include more description in the commit log in my next rev.
>
> As I replied when I did it -- I've applied the patches, so respinning
> won't work. Instead, please follow up with incremental fixes to this
> series instead.
>
>
> Thanks,
>
> -Olof
>
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
index fdd0c96..5c73117 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -55,8 +55,12 @@ 
 		#size-cells = <2>;
 		ranges;
 
-		/* DDR range is 40-bit addressing */
-		dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
+		/*
+		 * dma-ranges is 40-bit address space containing:
+		 * - GICv2m MSI register is at 0xe0080000
+		 * - DRAM range [0x8000000000 to 0xffffffffff]
+		 */
+		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
 
 		/include/ "amd-seattle-clks.dtsi"
 
@@ -159,7 +163,7 @@ 
 				<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
 
 			dma-coherent;
-			dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
+			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
 			ranges =
 				/* I/O Memory (size=64K) */
 				<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,