From patchwork Wed Feb 10 01:54:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 8267891 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D1CE8BEEE5 for ; Wed, 10 Feb 2016 01:56:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7DDF202C8 for ; Wed, 10 Feb 2016 01:56:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E446A2027D for ; Wed, 10 Feb 2016 01:56:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTJzv-0003Cy-NJ; Wed, 10 Feb 2016 01:55:15 +0000 Received: from mail-qg0-x234.google.com ([2607:f8b0:400d:c04::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTJzj-0002Mz-W8 for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2016 01:55:05 +0000 Received: by mail-qg0-x234.google.com with SMTP id y89so4321466qge.2 for ; Tue, 09 Feb 2016 17:54:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NRCmEvUU9h5KaM/THpz9Qvrw7W/qeavqhCo9XgOkXSU=; b=lRKpTXuvzwUUgze50tP1Xm4VT+KLCIobzC+f34RpoeF8r0ITdq16HaszbTGcxCvxAR zS2F8v82IqvHQKadmrU/F78tcy1o6DDGIFb3aPEcpP4ecAmJqcl/SenuW9lPGDQj7/HU il1wZ3iLsv3Ko6CcT1tgiVGUPXUMAXjbtTBjS5DAeLcWphYqP73V09hdc1qRESrTKmom Ye6WGPoNol94LotmjzOOzY2arJJs6+UqpCGDe+JFbS0CujoMvh0SwU6IKT9FaNC7ACFH TtKiHNDnggfS7j7LXSAs3tbHXcjmnZSFvrnW/Lr4+LtMzxosFwHlIJnl69CI249YrtJe 1rMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NRCmEvUU9h5KaM/THpz9Qvrw7W/qeavqhCo9XgOkXSU=; b=BcdzRUmuHUxZ3PkYhmioy2X6KDHsOuwm03g+GKaSMQyv80bOjqaQ8R7JolMIakQPYz z71O+yvvIppFs/xtpEIQexyZg3GgTnwtJEmymFoo46eYcjBKyPBtxM34XoQF8nsTcjNd XyPY1QvX0c2GgxoDG4cmtx5F91REYiqO9NaJ1ZjpCSWBQCnZdpj65MppI5Tfsqov2ioD qugemscKmHxbhrxlN4tHFeF0RDNc+oXzYnpGlkivLZFDDX2jmOIGcs1UvhIw9KhuKqS9 V6hAAh1lohXtVtY+Yd4qkNmf4wguP6PS1q09PG/Xh41HwNhMi7B0lQ1YE7dHHDjFV/0N ha3A== X-Gm-Message-State: AG10YOSbnbY8EwkPVEM5lvRsG1/sIr44SpoM2fPj1g3HIGQvXLUT7Viwf5YTnpFhPoq2EQ== X-Received: by 10.140.16.225 with SMTP id 88mr46464410qgb.96.1455069283031; Tue, 09 Feb 2016 17:54:43 -0800 (PST) Received: from localhost.localdomain ([190.2.108.156]) by smtp.gmail.com with ESMTPSA id e187sm390549qka.1.2016.02.09.17.54.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 Feb 2016 17:54:41 -0800 (PST) From: Ezequiel Garcia To: Subject: [PATCH v2 1/3] clocksource/drivers/lpc32xx: Don't use the prescaler counter for clockevents Date: Tue, 9 Feb 2016 22:54:25 -0300 Message-Id: <1455069267-4784-2-git-send-email-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1455069267-4784-1-git-send-email-ezequiel@vanguardiasur.com.ar> References: <1455069267-4784-1-git-send-email-ezequiel@vanguardiasur.com.ar> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160209_175504_275312_C1B1C8AC X-CRM114-Status: GOOD ( 14.24 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ezequiel Garcia , Thomas Gleixner , Daniel Lezcano , Joachim Eastwood , Vladimir Zapolskiy MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This commit switches the clockevents one-shot current implementation to avoid using the prescaler counter. The clockevents timer currently uses MR0=1, PR=ticks; and after this commit is uses MR0=ticks, PR=0. While using the prescaler with PR=1 works fine in one-shot mode, it seems it doesn't work as expected in periodic mode. By using the only match channel register (MR0) for the timer we make the periodic mode introduction easier, and consistent with one-shot mode. Signed-off-by: Ezequiel Garcia Reviewed-by: Joachim Eastwood Tested-by: Joachim Eastwood --- drivers/clocksource/time-lpc32xx.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/clocksource/time-lpc32xx.c b/drivers/clocksource/time-lpc32xx.c index 1316876b487a..50d1a63cbe1e 100644 --- a/drivers/clocksource/time-lpc32xx.c +++ b/drivers/clocksource/time-lpc32xx.c @@ -60,14 +60,13 @@ static int lpc32xx_clkevt_next_event(unsigned long delta, container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev); /* - * Place timer in reset and program the delta in the prescale - * register (PR). When the prescale counter matches the value - * in PR the counter register is incremented and the compare - * match will trigger. After setup the timer is released from - * reset and enabled. + * Place timer in reset and program the delta in the match + * channel 0 (MR0). When the timer counter matches the value + * in MR0 register the match will trigger an interrupt. + * After setup the timer is released from reset and enabled. */ writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); - writel_relaxed(delta, ddata->base + LPC32XX_TIMER_PR); + writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); return 0; @@ -210,13 +209,13 @@ static int __init lpc32xx_clockevent_init(struct device_node *np) /* * Disable timer and clear any pending interrupt (IR) on match - * channel 0 (MR0). Configure a compare match value of 1 on MR0 - * and enable interrupt, reset on match and stop on match (MCR). + * channel 0 (MR0). Clear the prescaler as it's not used. + * Enable interrupt, reset on match and stop on match (MCR). */ writel_relaxed(0, base + LPC32XX_TIMER_TCR); + writel_relaxed(0, base + LPC32XX_TIMER_PR); writel_relaxed(0, base + LPC32XX_TIMER_CTCR); writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR); - writel_relaxed(1, base + LPC32XX_TIMER_MR0); writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | LPC32XX_TIMER_MCR_MR0S, base + LPC32XX_TIMER_MCR);