From patchwork Wed Feb 10 01:54:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 8267881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 40D249F38B for ; Wed, 10 Feb 2016 01:56:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3D74A202D1 for ; Wed, 10 Feb 2016 01:56:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3E6020270 for ; Wed, 10 Feb 2016 01:56:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTK07-0003oe-0U; Wed, 10 Feb 2016 01:55:27 +0000 Received: from mail-qk0-x235.google.com ([2607:f8b0:400d:c09::235]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTJzn-0002Nx-3v for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2016 01:55:08 +0000 Received: by mail-qk0-x235.google.com with SMTP id x1so2167431qkc.1 for ; Tue, 09 Feb 2016 17:54:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KNg5XJvupRwQXjZfmo9fVRZ5gl/nK7s2sBrPxRD2UU4=; b=F5fbUl0WWOmM1NJiQrfZZ0myvfc9w6KHPlu07Lxh/Dg7Q+FbOnMGj4jQ+7hLnpSWW5 0GQwZ9JWzz8LXhvu6jrEbffmJgGjov1uFWDc+Jl6qwWj/oKTuZ1j05rNh4WAG8XqpJQc XepqsKmahfj3mTgsVgewfi3PCZKoxSaOtKxI+0qPl0GiDw+40CUHXiHGIUAuFp19cHhk zjATfX/AxAwUXpSwQEq8MgT9WML1zwaoZIOXTZJxya1ZKRClkWIYqMx9KxsMaxX/G+oT tpGzfdgLShr7evcHWLaEUfgEZoZKlghAfmW3q4Xi4ZtJdcQKEpud+TwKZRxQOSqXEDhC INtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KNg5XJvupRwQXjZfmo9fVRZ5gl/nK7s2sBrPxRD2UU4=; b=bzAmJVObaBrDH3gfahkV7CCfsz7y4z764tCWEAil311cgVwcy4xVvjGeodigquv3sh cJdo9qMdRurwxdtkmTTzxVSFPNfSbrLsFDfvNEQwkzK+o06vtI64sTGCvN/RN/o8aCso 6QHK9sAuSl+r3yAub7qqNTStbr9iHlZXoTqosBoOboRwgQRid9Kij9ZoQiGpg/6ZpvSj +iw55vZULc0v+Uzr7JHRE7rZAQdJkXB9Ep3a1Bo0ylJkWq5hN/NYHZU401B2Tesak3tq 2IktZYCIRSebx1rOkwK2oVx3tw+2Cl2drdwioVkhVmcoZcvQw2AvjG4pSKuvzDM3UuC8 sc8A== X-Gm-Message-State: AG10YOTpq6juWxR7r3NRAAyGJxKHI9UZWWJ+htrFH4AciExob5ZfkYwT3wG89qEr3o03Gg== X-Received: by 10.55.21.151 with SMTP id 23mr25275823qkv.33.1455069286144; Tue, 09 Feb 2016 17:54:46 -0800 (PST) Received: from localhost.localdomain ([190.2.108.156]) by smtp.gmail.com with ESMTPSA id e187sm390549qka.1.2016.02.09.17.54.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 Feb 2016 17:54:44 -0800 (PST) From: Ezequiel Garcia To: Subject: [PATCH v2 2/3] clocksource/drivers/lpc32xx: Support periodic mode Date: Tue, 9 Feb 2016 22:54:26 -0300 Message-Id: <1455069267-4784-3-git-send-email-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1455069267-4784-1-git-send-email-ezequiel@vanguardiasur.com.ar> References: <1455069267-4784-1-git-send-email-ezequiel@vanguardiasur.com.ar> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160209_175507_375556_4CFF81DB X-CRM114-Status: GOOD ( 16.56 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ezequiel Garcia , Thomas Gleixner , Daniel Lezcano , Joachim Eastwood , Vladimir Zapolskiy MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds the support for periodic mode. This is done by not setting the MR0S (Stop on TnMR0) bit on MCR, thus allowing interrupts to be periodically generated on MR0 matches. In order to do this, move the initial configuration that is specific to the one-shot mode to set_state_oneshot(). Signed-off-by: Ezequiel Garcia Reviewed-by: Joachim Eastwood Tested-by: Joachim Eastwood --- drivers/clocksource/time-lpc32xx.c | 39 +++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/time-lpc32xx.c b/drivers/clocksource/time-lpc32xx.c index 50d1a63cbe1e..5694eddade15 100644 --- a/drivers/clocksource/time-lpc32xx.c +++ b/drivers/clocksource/time-lpc32xx.c @@ -43,6 +43,7 @@ struct lpc32xx_clock_event_ddata { struct clock_event_device evtdev; void __iomem *base; + u32 ticks_per_jiffy; }; /* Needed for the sched clock */ @@ -85,11 +86,39 @@ static int lpc32xx_clkevt_shutdown(struct clock_event_device *evtdev) static int lpc32xx_clkevt_oneshot(struct clock_event_device *evtdev) { + struct lpc32xx_clock_event_ddata *ddata = + container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev); + /* * When using oneshot, we must also disable the timer * to wait for the first call to set_next_event(). */ - return lpc32xx_clkevt_shutdown(evtdev); + writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); + + /* Enable interrupt, reset on match and stop on match (MCR). */ + writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | + LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR); + return 0; +} + +static int lpc32xx_clkevt_periodic(struct clock_event_device *evtdev) +{ + struct lpc32xx_clock_event_ddata *ddata = + container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev); + + /* Enable interrupt and reset on match. */ + writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R, + ddata->base + LPC32XX_TIMER_MCR); + + /* + * Place timer in reset and program the delta in the match + * channel 0 (MR0). + */ + writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); + writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); + writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); + + return 0; } static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id) @@ -107,11 +136,13 @@ static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id) static struct lpc32xx_clock_event_ddata lpc32xx_clk_event_ddata = { .evtdev = { .name = "lpc3220 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC, .rating = 300, .set_next_event = lpc32xx_clkevt_next_event, .set_state_shutdown = lpc32xx_clkevt_shutdown, .set_state_oneshot = lpc32xx_clkevt_oneshot, + .set_state_periodic = lpc32xx_clkevt_periodic, }, }; @@ -210,17 +241,15 @@ static int __init lpc32xx_clockevent_init(struct device_node *np) /* * Disable timer and clear any pending interrupt (IR) on match * channel 0 (MR0). Clear the prescaler as it's not used. - * Enable interrupt, reset on match and stop on match (MCR). */ writel_relaxed(0, base + LPC32XX_TIMER_TCR); writel_relaxed(0, base + LPC32XX_TIMER_PR); writel_relaxed(0, base + LPC32XX_TIMER_CTCR); writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR); - writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | - LPC32XX_TIMER_MCR_MR0S, base + LPC32XX_TIMER_MCR); rate = clk_get_rate(clk); lpc32xx_clk_event_ddata.base = base; + lpc32xx_clk_event_ddata.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ); clockevents_config_and_register(&lpc32xx_clk_event_ddata.evtdev, rate, 1, -1);