From patchwork Wed Feb 10 13:22:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoine Tenart X-Patchwork-Id: 8272001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AAFE8BEEED for ; Wed, 10 Feb 2016 13:25:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DFDF1203B4 for ; Wed, 10 Feb 2016 13:25:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA9A0203AE for ; Wed, 10 Feb 2016 13:25:08 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTUkE-0002ds-24; Wed, 10 Feb 2016 13:23:46 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTUju-0002Ob-9E for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2016 13:23:28 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 337C52B2; Wed, 10 Feb 2016 14:23:06 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-20-139.w83-193.abo.wanadoo.fr [83.193.84.139]) by mail.free-electrons.com (Postfix) with ESMTPSA id F2870B2; Wed, 10 Feb 2016 14:23:05 +0100 (CET) From: Antoine Tenart To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, tsahee@annapurnalabs.com Subject: [PATCH v2 3/7] Documentation: bindings: document the Alpine MSIX driver Date: Wed, 10 Feb 2016 14:22:59 +0100 Message-Id: <1455110583-19515-4-git-send-email-antoine.tenart@free-electrons.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1455110583-19515-1-git-send-email-antoine.tenart@free-electrons.com> References: <1455110583-19515-1-git-send-email-antoine.tenart@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160210_052326_620576_5166C3EF X-CRM114-Status: GOOD ( 11.81 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.petazzoni@free-electrons.com, Antoine Tenart , linux-arm-kernel@lists.infradead.org, rshitrit@annapurnalabs.com, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Following the addition of the Alpine MSIX driver, this patch adds the corresponding bindings documentation. Signed-off-by: Antoine Tenart Signed-off-by: Tsahee Zidenberg --- .../interrupt-controller/al,alpine-msix.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt new file mode 100644 index 000000000000..c7d3d0192f5d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt @@ -0,0 +1,24 @@ +Alpine MSIX controller + +Required properties: + +- compatible: should be "al,alpine-msix" +- reg: physical base address and size of the registers +- interrupt-parent: specifies the parent interrupt controller. +- interrupt-controller: identifies the node as an interrupt controller +- msi-controller: identifies the node as an PCI Message Signaled Interrupt + controller +- al,msi-base-spi: SPI base of the MSI frame +- al,msi-num-spis: number of SPIs assigned to the MSI frame + +Example: + +msix: msix { + compatible = "al,alpine-msix"; + reg = <0x0 0xfbe00000 0x0 0x100000>; + interrupt-parent = <&gic>; + interrupt-controller; + msi-controller; + al,msi-base-spi = <160>; + al,msi-num-spis = <160>; +};