From patchwork Thu Feb 18 18:29:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tirumalesh Chalamarla X-Patchwork-Id: 8353441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4E7F69F727 for ; Thu, 18 Feb 2016 18:31:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 45AC2202EB for ; Thu, 18 Feb 2016 18:31:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 228AD20263 for ; Thu, 18 Feb 2016 18:31:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWTL6-0000np-Ru; Thu, 18 Feb 2016 18:30:08 +0000 Received: from mail-bn1bon0095.outbound.protection.outlook.com ([157.56.111.95] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWTKo-0008FX-7J for linux-arm-kernel@lists.infradead.org; Thu, 18 Feb 2016 18:29:53 +0000 Authentication-Results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=caviumnetworks.com; Received: from tiru-pc.caveonetworks.com (64.2.3.194) by SN1PR0701MB1790.namprd07.prod.outlook.com (10.162.100.144) with Microsoft SMTP Server (TLS) id 15.1.409.15; Thu, 18 Feb 2016 18:29:27 +0000 From: To: , Subject: [PATCH V2] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704 Date: Thu, 18 Feb 2016 10:29:18 -0800 Message-ID: <1455820158-8529-1-git-send-email-tchalamarla@caviumnetworks.com> X-Mailer: git-send-email 2.1.0 MIME-Version: 1.0 X-Originating-IP: [64.2.3.194] X-ClientProxiedBy: CY1PR21CA0075.namprd21.prod.outlook.com (25.163.250.171) To SN1PR0701MB1790.namprd07.prod.outlook.com (25.162.100.144) X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1790; 2:g/o1lBA3SP6fmK2L3BMAeSru/uyt6ZprVnkqDCxWEJ/fmWEWxlxEC04h5js1DnxTzK7XD0B6yD261vlnWRAFyl1emuuM7mnvarIw3M6jAXKizvgMun3lrnT5rExxKclDjriutRHJQTs1f3L5RPtlzA==; 3:k3WLBbj0U507KG6hph1ditYUPDpkTSHMPM55+C4XXdBlNFagKaohWYF3LEenuDMfzenDTTW1iafvtEuqHnXTUMvrH+mo0WCVKyidhdU2IwQK/4arOAuSmYqP3VMB/91V; 25:sQz+5+iHQr6j7AfyCPdGwoqT13kp3FGlgLT0afH4Z+RC/jIVgGCg8iVOAg6KjVkVgbylfjLjZLTFgJKoQIj1a/FMWLnX65Zi2gT6XA97NCYPk1DBPCOICV5Wy4SzJoEgrxMk9Awx293hhiWD+vrvXnjpWdsqS+1YQkeSU2A27suolIu5qv+K0Tc4NUuOuIn/hQ+z0u0GqAax8rImeSbdFWCGJXq5fCtWWwp3IPjAE3sYY4OhPrOCIsqiFMYuIssngCgxXEGFh0GHryy2A5q55MgKVnIGiY8frou+Xgay91Tq9iI3+UKjK9pXdozlA35X X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SN1PR0701MB1790; X-MS-Office365-Filtering-Correlation-Id: 174bf453-cf26-43bc-073a-08d338916f78 X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1790; 20:ULAWUvH/OBoBW8a6pDn9+1VC6Jx+FynAcSDIeMIdKByE9hwg4kR0tOYIUAgRirKTwdklCuKLhST4A2Vt3e5E++oKdL5JcqcZzw8TlZO8WYwS7NbwxyM/KnVPCkUM83Q3Dx2iQeTC+9z065FoyI4xWzlo8EwWVg8z9ZiZqDPPD7Qc04Bz4gT57hae1DzGQ3f6Mb1n7SekDyteMvHMoPLXMw2OGXtETwyABeOhABkmCPXGosAHkR/PQ+HlLrkTn3ejxBb1cUABrkNMJB/Uk7NEhOoHuyub14wRdHEhKH6w5b93KJvM8TVogBoI7TiM+e0LJIKtdywDD38tbyLWQ3JCdwtMs7/f45R4H2P/JNXTmHo+D1BpoqN90JY268yykS27zdBmG4tDnUOVjHRyRTFaOUu1HxaqIRHFE1rmpLMowy/rwZvKTZ1I0pSGYNIGJz5fr6UIOF6asn53uYS1d0GahSJs5+s8X9HRerBpJcD06c3+LhE1ATEA2+U5pf8WHsyOgKliZg4wouQCSC3FVYylwmHA7NN4qNh9xZcawsEvUDIuRuzx2wwAqDFh3Bj+rmV+VPeT+jWUs9RAN+VM86n+553H0WUmgZuWjUPaztax3Xc= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(8121501046)(5005006)(3002001)(10201501046); SRVR:SN1PR0701MB1790; BCL:0; PCL:0; RULEID:; SRVR:SN1PR0701MB1790; X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1790; 4:JcCMOta15Pwxea1qMGCMgcsfk4EtHlKFz7/PAY1+3X87vflYxaf/Q7ZMnSuRRiHRxS8/Dz2k7Iy9CfQph7sAJirYfyr6QHHKOsxLrk3gcfZ0Y9x+/rZIX+TaAJpun2lXgh/7mld11zczK8QzuieUjWU9fRaXcqdi9uT5gXE0fx8mVlsbf9IY+udcdV8kRP9pnvn+VnR7ICS6X69BteGqmHzAmpfMV8uKSt7dm2o96ZjMGV9Sz7igVbklQkvsev3mQFT1rUKqbd5Ix1JbebfSFOA4ypR53gpi6rVdMAAAQpWCCxtK/F/wW03VK2lQ2MgeOxQjs7pT+LVQfBzhJeE/9ZQ4vBS2HJbX8NMPul3RI/bRfdHj1bIMN8xGoPRc+qpW X-Forefront-PRVS: 085634EFF4 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(6009001)(53416004)(5003940100001)(42186005)(5008740100001)(86152002)(50466002)(92566002)(47776003)(66066001)(50986999)(36756003)(229853001)(2876002)(4326007)(77096005)(2906002)(48376002)(4001430100002)(5004730100002)(107886002)(5001960100002)(189998001)(230783001)(5001770100001)(50226001)(122386002)(19580405001)(6116002)(3846002)(1096002)(19580395003)(586003)(33646002)(40100003); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1PR0701MB1790; H:tiru-pc.caveonetworks.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; SN1PR0701MB1790; 23:Wz9LLhYZJooslKsxH8GOEGvCFFQbltFiqx27qsE?= =?us-ascii?Q?0dtOLtLCx2EDEnrMphB39De0cdMho3Kkty/pGnYqjMccASzPbJVm4kdtTVkj?= =?us-ascii?Q?fAbF6/IKtR4fl4Pfzvz/eu+GzzFEIaU2S42mY+8gGCnOJM5JxBzzsdxSd2CW?= =?us-ascii?Q?G1EcXo5qKhd9pUt02PbzBM30ohU2NAS8OOqnbmkylUh6vW+WEfBm31bWF2ZO?= =?us-ascii?Q?RCqXQ4SHJAT+Dg4jFzfiTVjUtcY1bc/BGqOA1JMNFBmXHzkUp1UvjtiW7rbh?= =?us-ascii?Q?PJHMMvl5eyNQexUBwfmli1BUrFaOHfvZ94/6ILNFmdeN5kXJBuVWPJ/JyQMW?= =?us-ascii?Q?53Z7druaSIA+V4c9+SknLvevEerPxJFJH81mXmYH9JhI0gQfkxz4dX1H/mW4?= =?us-ascii?Q?3oFBthMAGgdPGJgJUsnKiujvb29fhgRKJzPar8lGS6phrttOkFVBUrH6gLk9?= =?us-ascii?Q?fZWuJ2QfoglD1VKMMwmKdzZTc5qSEOOldDmqqiTXImTHoyHbMW4h1HcOhiQ1?= =?us-ascii?Q?xKGfKhouqW6tADhJQ9la7uXMho2xD78MUMIdHFRIgBUNoxjkriT3HQgIXIbO?= =?us-ascii?Q?gQOQNSxShuN8WYXqhMTWlhaR4q8fmIQo8xwp/z2KolNeKa52sMPDWzBWigV6?= =?us-ascii?Q?/nSIJ7Rql87VvpWaXl5XqPHP1UW5D+c5MGG14i+NezpGUz6Uq2qRbdhJknGT?= =?us-ascii?Q?2SXEjxfs6e8b+IhM0yx6vGHqXfMwGp23Qlx9a1HtjIviNrXeWj5Jyn5ag37I?= =?us-ascii?Q?5XtgKRTT0uGWxbXf0MNLA9qW22lWmyHDj1z+M6uPtP01db10N5VqWWD7aVbl?= =?us-ascii?Q?unud5VFqEzd0G0i0kuFTKUnY9YeZH3VkSJNIpKew+QZOQRtm6qa+9PF2zOCA?= =?us-ascii?Q?CRrLkYAo3l70FZFr+eI6RlTknRR3rW7JbQqwZTBceAqJGd4hwViYt0bG6bSV?= =?us-ascii?Q?v5IRunemUAvDc5TvZmBYqOE8J0anxt6xhe3cICHpfOA=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1790; 5:WXfvWpXw/W7RYmJms690xlo0WbuBbZdQy1mwHeq06d8HfiqTiIbxIVgRBMnpoqiRH0zWC1b1KTLJt0jb3yIuI+GXyPSTcz15jrlpNdomjngH+5JvipFlz6hMjXs32O0lkRwruewp3JAJY0yshfneIw==; 24:ERNBjh/jWbHT2Kz5eowxWaabI7LlcFKJ/sMRM9aUefL3WgWvYYvBi9ZyogMHVoAWr+ugOMIpm9b9xi9WSVBgKEP8kccu9tgUXhVlepKWMHw= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2016 18:29:27.6078 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR0701MB1790 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160218_102950_965998_A1CDC887 X-CRM114-Status: UNSURE ( 9.16 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: iommu@lists.linux-foundation.org, Geethasowjanya.Akula@caviumnetworks.com, linux-arm-kernel@lists.infradead.org, tchalamarla@caviumnetworks.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tirumalesh Chalamarla Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3. This patch tries to address these issuee by supplying asid and vmid base from devicetree. changes from V1: - rebased on top of 16 bit VMID patch - removed redundent options from DT - insted of transform, DT now supplies starting ASID/VMID Signed-off-by: Akula Geethasowjanya Signed-off-by: Tirumalesh Chalamarla --- .../devicetree/bindings/iommu/arm,smmu.txt | 8 +++++ drivers/iommu/arm-smmu.c | 37 +++++++++++++++------- 2 files changed, 34 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index bb7e569..80b8484 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -57,6 +57,14 @@ conditions. - smmu-enable-vmid16 : Enable 16 bit VMID, if allowed. +- asid-base : Buggy SMMUv2 implementations which doesn't satisfy the + ASID namespace needs, use this field to specify starting + ASID for the SMMU. + +- vmid-base : Buggy SMMUv2 implementations which doesn't satisfy the VMID + namespace needs, use this field to specify starting VMID + for the SMMU. + Example: smmu { diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 003c442..dc46b9a 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -320,6 +320,9 @@ struct arm_smmu_device { unsigned long ipa_size; unsigned long pa_size; + u32 asid_base; + u32 vmid_base; + u32 num_global_irqs; u32 num_context_irqs; unsigned int *irqs; @@ -335,8 +338,8 @@ struct arm_smmu_cfg { }; #define INVALID_IRPTNDX 0xff -#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) -#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) +#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)((smmu)->asid_base + (cfg)->cbndx)) +#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)((smmu)->vmid_base + (cfg)->cbndx)) enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, @@ -576,11 +579,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) if (stage1) { base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); - writel_relaxed(ARM_SMMU_CB_ASID(cfg), + writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg), base + ARM_SMMU_CB_S1_TLBIASID); } else { base = ARM_SMMU_GR0(smmu); - writel_relaxed(ARM_SMMU_CB_VMID(cfg), + writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), base + ARM_SMMU_GR0_TLBIVMID); } @@ -602,7 +605,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) { iova &= ~12UL; - iova |= ARM_SMMU_CB_ASID(cfg); + iova |= ARM_SMMU_CB_ASID(smmu, cfg); do { writel_relaxed(iova, reg); iova += granule; @@ -610,7 +613,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, #ifdef CONFIG_64BIT } else { iova >>= 12; - iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48; + iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48; do { writeq_relaxed(iova, reg); iova += granule >> 12; @@ -630,7 +633,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, #endif } else { reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; - writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); + writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg); } } @@ -744,7 +747,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, #endif /* if 16bit VMID required set VMID in CBA2R */ if (smmu->options & ARM_SMMU_OPT_ENABLE_VMID16) - reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT; + reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT; writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); } @@ -763,7 +766,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); } else if (!(smmu->options & ARM_SMMU_OPT_ENABLE_VMID16)) { /*16 bit VMID is not enabled set 8 bit VMID here */ - reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; + reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT; } writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); @@ -771,11 +774,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, if (stage1) { reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; - reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; + reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0); reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; - reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; + reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1); } else { reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; @@ -1812,6 +1815,18 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev) parse_driver_options(smmu); + if (of_property_read_u32(dev->of_node, "#asid-base", + &smmu->asid_base)) { + smmu->asid_base = 0; + } + + if (of_property_read_u32(dev->of_node, "#vmid-base", + &smmu->vmid_base)) { + smmu->vmid_base = 1; + } + if (smmu->vmid_base == 0) + smmu->vmid_base = 1; + if (smmu->version > ARM_SMMU_V1 && smmu->num_context_banks != smmu->num_context_irqs) { dev_err(dev,