From patchwork Fri Feb 19 15:22:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoine Tenart X-Patchwork-Id: 8362071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 08885C0553 for ; Fri, 19 Feb 2016 15:25:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 289672045B for ; Fri, 19 Feb 2016 15:25:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B1F520458 for ; Fri, 19 Feb 2016 15:25:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWmu7-0001SZ-Np; Fri, 19 Feb 2016 15:23:35 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWmtl-0001L6-Te for linux-arm-kernel@lists.infradead.org; Fri, 19 Feb 2016 15:23:15 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id C4BEA17C1; Fri, 19 Feb 2016 16:22:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-984-111.w86-217.abo.wanadoo.fr [86.217.138.111]) by mail.free-electrons.com (Postfix) with ESMTPSA id 914D711E; Fri, 19 Feb 2016 16:22:51 +0100 (CET) From: Antoine Tenart To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, tsahee@annapurnalabs.com Subject: [PATCH v3 3/7] Documentation: bindings: document the Alpine MSIX driver Date: Fri, 19 Feb 2016 16:22:45 +0100 Message-Id: <1455895369-13187-4-git-send-email-antoine.tenart@free-electrons.com> X-Mailer: git-send-email 2.7.1 In-Reply-To: <1455895369-13187-1-git-send-email-antoine.tenart@free-electrons.com> References: <1455895369-13187-1-git-send-email-antoine.tenart@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160219_072314_239797_9105D6F7 X-CRM114-Status: GOOD ( 12.36 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.petazzoni@free-electrons.com, Antoine Tenart , linux-arm-kernel@lists.infradead.org, rshitrit@annapurnalabs.com, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Following the addition of the Alpine MSIX driver, this patch adds the corresponding bindings documentation. Signed-off-by: Antoine Tenart Signed-off-by: Tsahee Zidenberg --- .../interrupt-controller/al,alpine-msix.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt new file mode 100644 index 000000000000..f6f1c14bf99b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt @@ -0,0 +1,26 @@ +Alpine MSIX controller + +See arm,gic-v3.txt for SPI and MSI definitions. + +Required properties: + +- compatible: should be "al,alpine-msix" +- reg: physical base address and size of the registers +- interrupt-parent: specifies the parent interrupt controller. +- interrupt-controller: identifies the node as an interrupt controller +- msi-controller: identifies the node as an PCI Message Signaled Interrupt + controller +- al,msi-base-spi: SPI base of the MSI frame +- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 + +Example: + +msix: msix { + compatible = "al,alpine-msix"; + reg = <0x0 0xfbe00000 0x0 0x100000>; + interrupt-parent = <&gic>; + interrupt-controller; + msi-controller; + al,msi-base-spi = <160>; + al,msi-num-spis = <160>; +};