From patchwork Wed Feb 24 19:37:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tirumalesh Chalamarla X-Patchwork-Id: 8411551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 131209F372 for ; Wed, 24 Feb 2016 19:39:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0E3C320361 for ; Wed, 24 Feb 2016 19:39:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9BFDC202EB for ; Wed, 24 Feb 2016 19:39:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYfFi-0002UR-SC; Wed, 24 Feb 2016 19:37:38 +0000 Received: from mail-bn1on0066.outbound.protection.outlook.com ([157.56.110.66] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYfFf-0002M1-0T for linux-arm-kernel@lists.infradead.org; Wed, 24 Feb 2016 19:37:36 +0000 Authentication-Results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=caviumnetworks.com; Received: from tiru-pc.caveonetworks.com (64.2.3.194) by CY1PR0701MB1786.namprd07.prod.outlook.com (10.163.42.144) with Microsoft SMTP Server (TLS) id 15.1.415.20; Wed, 24 Feb 2016 19:37:12 +0000 From: Tirumalesh Chalamarla To: , , Subject: [PATCH V3] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704 Date: Wed, 24 Feb 2016 11:37:00 -0800 Message-ID: <1456342620-3138-1-git-send-email-tchalamarla@caviumnetworks.com> X-Mailer: git-send-email 2.1.0 MIME-Version: 1.0 X-Originating-IP: [64.2.3.194] X-ClientProxiedBy: CY1PR12CA0045.namprd12.prod.outlook.com (25.163.230.13) To CY1PR0701MB1786.namprd07.prod.outlook.com (25.163.42.144) X-Microsoft-Exchange-Diagnostics: 1; CY1PR0701MB1786; 2:Ck65wQO6JGFSUNc7Vha0hjJjooGIA0FhjgGryz9PQKDSWle8l7oGCLpB+A0dIrjsP0hxMA4fmyl4lpjvedTjc053QlcWptnxFW04WgFJNipGIoWHR/LpJx5g6+MGr+s3/eG0CYxedbDevSmze1UVhw==; 3:m5ABfA7sIUcxWAshZ20ZEKU97GIPvBJrTtgBeqym68L9t4QP/2uDKRCI3miwH9fpRwRR0Fqc/s1d6Y49KGk2+uF0C90K4RH8VsNOsi7i4Ki4eTUF0QuKxs+5Jk5RPl7u; 25:/xf2dq7M8Q4qpwQNgbcfbKbnpPlbWWg7QktwO5/XCPthO7cLy19m0inNdq9dCtmg8XVh8ZANohseCuTjDegXdkL/XgLznR3afoKFtQTMw4f8ahvLJ0/lKR3NmCfULeyZLTdcitZA7ynxjzpb2j4epdBUgQnYR5Fw9Sqw3Z+3M9+LDM2a+STYZOhlrI52bdsAsTTia3ZiyGnL6uIeFmQRB3r00wsth1bC+dpbDunJBtZk2TbfkzOn7em9C/hdi8EbKHhjb82eWnfsm5PjWNpNy3BE34KNIs88hyvgTPht4/hJaRXo35GdTnfpd+8VbjZ4 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0701MB1786; X-MS-Office365-Filtering-Correlation-Id: fe320f8b-57b9-4c59-780a-08d33d51e48b X-Microsoft-Exchange-Diagnostics: 1; CY1PR0701MB1786; 20:s5XTrmJAmtVKwzigQewhtKzxGr5GoldoMhKfPLX3g+dnhOY3gNHFQ2IUJjlyBDsVugs6hA5VAgTHYs+9yQbk1Z+uWhaJS26hmYuGBy+y/2/GNPEIjgUWOds0EYftr5PHsJXD7IBMjvW3/5G0IPbiHBKSNqNWElvLQFEhRWzN1lMDvT8MxwYSjPNGjajIDIvvlhsQIKxBXpnBo2hZ30+gC8M+jJDVNqTMiZxr51CGRus2+QpwDBDpb0gmn6pCvflRImcC1mwRkDiyKXAAsFRf8i7F/QH+95oNLIpKb7xRt8DJEqgBLuve6OPnse2I1IGlZhk4hx4QRGG+M2PM+Vul6G8kETBEhQAM48v9HYlwcva8p9RBdtnz/RCwvxrSvkt+Me/Q5D45kyDK+ybjGVSN82EZ+yg4AOXgCDJ+WISZRUBULhpBQu3VcH2P2Wk7+C9A6JqPShChpYyswp0t/5kCm94EEzys+30tp/21ygzreGmgDaP2WmEHRLGgkDnEt8CLQk5w2g3S9UAAqcAyVZ4AEnMGqZkElAnoZ4OfWudG9ht0rfWiR0t/m2lU4qMknF31iYZIM7PL1/q5xyTgupxZrt8gn9sIs1LKprGkQmCPz70= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046); SRVR:CY1PR0701MB1786; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0701MB1786; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0701MB1786; 4:9RuACz9ZxQ/5m7mnjxtKH00NTvyJpK9SciT1OjWpPKwUuuIeFfJk49efvo3/0B2KCyT1k7bN4XrhBLmHhipsDepcM3574TDZ4DePRYlSETpgx2WpVCSNJisqT/28KM+DmiU/hFxGo7qusTUv6xpb4PgDzlvUf7s9L6V+Za6Ic91To8xMMBh6kw+l5KnnasQVNauNbkTbyeH4t3UI9dHp8N1vpYtdOYY3OSDKysz8b+EQlswNUiv18ITfv1Gue6tE2MWQkmXyN9IhXpajKMlYoGS92YIFdUF0QsAiKry9KD8XsQN/fpi70IJdP5OBcD0W9LUCO+9ujwB05ujyoAacIIbO0T5T4Bt3rBxgvhJVovJOSmGPFST8mKmseYmC1B/y X-Forefront-PRVS: 08626BE3A5 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6009001)(122386002)(4001430100002)(50986999)(47776003)(66066001)(230783001)(33646002)(40100003)(50466002)(42186005)(53416004)(5003940100001)(50226001)(36756003)(5001770100001)(5008740100001)(5001960100002)(107886002)(189998001)(3846002)(586003)(6116002)(77096005)(1096002)(19580405001)(19580395003)(229853001)(5004730100002)(2906002)(48376002)(87976001)(92566002)(4326007)(2201001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR0701MB1786; H:tiru-pc.caveonetworks.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR0701MB1786; 23:w/azVCn1Z3M719A9HBxEnSPWxGhc69WszJi0/4O?= =?us-ascii?Q?1UdtaNuKlms4tjg5R7XTe3DhDurFCmfPXS3l6QhH7SKVUDcyUqbwP3cJnFo7?= =?us-ascii?Q?FdtXcW8iuqeT3aRHrOJu2N5ohZsa/tKahSHaVgxQPlPCOV603IuWjq1qBn4G?= =?us-ascii?Q?1VaMjATgOkd3wQcmbPza2c/gv+flx1AW5grCQPlmFCrzjfXOv2OP5lZDpBRE?= =?us-ascii?Q?kM51yY7eFQU8BLKCRjWA1wGIjUtrUYqXa8scQRpwmMOm+C/yBqyDuSfHFS5l?= =?us-ascii?Q?0ah0UvrWv3P3a4Yg8WESyyUkWLF4eVYRj4H76TqKCcud80DT4a7tHhL0prod?= =?us-ascii?Q?eWf36lGCX09zoGSkwGrmHE0RiLiwO/OWocp5b4l7mEQAEb8H+HzNInjvECQm?= =?us-ascii?Q?TBZCWGujZS5GPgAB7Tplsn/qXfHrVXvrAY6PDj/2+DU13yPILhMyytYQVjZU?= =?us-ascii?Q?41/l1pwv2664uSA3XrZ1bqzO67asj5GGdZHdTn+ZnTzei8gqmaw/RJoLRsid?= =?us-ascii?Q?htXDBqk9Y/HvO2kB3wQwi82pZypHFKF+OxTYD98IiucOkpubmGFjoSN45CQx?= =?us-ascii?Q?b1BAQTNPS6D1DtIsQKbmoTq5n0N6LCYqQ5QxJKLjaUqClrsCJgZVfcx4psY0?= =?us-ascii?Q?l44IP4KIihIjuBeGMR3lIZ3999czfmL9senxiIsyQazFXOSkznYPaBfiOltA?= =?us-ascii?Q?YbL31PUc+BQ+SwHJEXLQXRhbSi4R0ejtf8/mYMiAPDRt7OohTFmLN/FB+eCW?= =?us-ascii?Q?6SypycMg0QIZfc179x8N9FaLUpDlT64j7zo2UKvZygmJ2sWVENks/3jltCEa?= =?us-ascii?Q?EKTd5eKHpY4M0CyCrd2aAh5IJ/aQIcOjyOnJ9okDHrAuYPUQpyCYbLiOAhCX?= =?us-ascii?Q?5NCviMNU/F260KQ2GDe1deNc9fVDr5F7jO/dHbTekWb8kxPx1nXqpdMB5zSy?= =?us-ascii?Q?croBMqcX1YJXcmdWnwlFSSvF8Xgmy+rt9tsK/e5lhIocHTTHroTvqC2aLMFR?= =?us-ascii?Q?+RIYQp9IBUeb8OORS5ELLAqbf?= X-Microsoft-Exchange-Diagnostics: 1; CY1PR0701MB1786; 5:XqI25trS+EL62r2uKM+1Dxdi8KEo/whZZ1HiB/kWs9t34BuNWNjJwvNYw81pz4YNy3+pVTpxyfXgSsynNGJ67CIFDyLPxeXOPLYxBtWXue1i95koVeRD30Stf4f+0i0OsXFjT52MeDQiD5ANurgh+w==; 24:vK/TgJXAbMsIqAdHSal6ltyGrDLQJWMeqHhN/96jdNRlmljCV7K3XZUQf/7AV1WW7cramRlq6Qg+lj86ueR1hTk745ufci8Hf6U5sBEO3Ws= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2016 19:37:12.0831 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0701MB1786 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160224_113735_442170_CD7F3475 X-CRM114-Status: GOOD ( 12.22 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: iommu@lists.linux-foundation.org, Geethasowjanya.Akula@caviumnetworks.com, linux-arm-kernel@lists.infradead.org, tchalamarla@caviumnetworks.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3. This patch tries to address these issuee by supplying asid and vmid base from devicetree. changes from V2: - removed *_base from DT, and replaced with compatible string changes from V1: - rebased on top of 16 bit VMID patch - removed redundent options from DT - insted of transform, DT now supplies starting ASID/VMID Signed-off-by: Tirumalesh Chalamarla Signed-off-by: Akula Geethasowjanya --- .../devicetree/bindings/iommu/arm,smmu.txt | 1 + drivers/iommu/arm-smmu.c | 48 +++++++++++++++++----- 2 files changed, 38 insertions(+), 11 deletions(-) -- 2.1.0 diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 7180745..19fe6f2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -16,6 +16,7 @@ conditions. "arm,mmu-400" "arm,mmu-401" "arm,mmu-500" + "cavium,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 247a469..f2287a5 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -326,6 +326,12 @@ struct arm_smmu_device { struct list_head list; struct rb_root masters; + /* + *The follwoing fields are specific to Cavium, Thunder + */ + u32 cavium_smmu_id; + u32 cavium_id_base; + }; struct arm_smmu_cfg { @@ -335,8 +341,8 @@ struct arm_smmu_cfg { }; #define INVALID_IRPTNDX 0xff -#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) -#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) +#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx) +#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1) enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, @@ -364,6 +370,8 @@ struct arm_smmu_option_prop { const char *prop; }; +static int cavium_smmu_count; + static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, { 0, NULL}, @@ -575,11 +583,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) if (stage1) { base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); - writel_relaxed(ARM_SMMU_CB_ASID(cfg), + writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg), base + ARM_SMMU_CB_S1_TLBIASID); } else { base = ARM_SMMU_GR0(smmu); - writel_relaxed(ARM_SMMU_CB_VMID(cfg), + writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), base + ARM_SMMU_GR0_TLBIVMID); } @@ -601,7 +609,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) { iova &= ~12UL; - iova |= ARM_SMMU_CB_ASID(cfg); + iova |= ARM_SMMU_CB_ASID(smmu, cfg); do { writel_relaxed(iova, reg); iova += granule; @@ -609,7 +617,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, #ifdef CONFIG_64BIT } else { iova >>= 12; - iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48; + iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48; do { writeq_relaxed(iova, reg); iova += granule >> 12; @@ -629,7 +637,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, #endif } else { reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; - writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); + writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg); } } @@ -738,7 +746,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, #endif /* if 16bit VMID supported set VMID in CBA2R */ if (smmu->features & ARM_SMMU_FEAT_VMID16) - reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT; + reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT; writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); } @@ -757,7 +765,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { /*16 bit VMID is not supported set 8 bit VMID here */ - reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; + reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT; } writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); @@ -765,11 +773,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, if (stage1) { reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; - reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; + reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0); reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; - reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; + reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1); } else { reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; @@ -1717,6 +1725,7 @@ static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, + { .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); @@ -1827,6 +1836,23 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev) } } + /* + * Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID + * namespaces; specifically within a given node SMMU0 and SMMU1 share, + * as does SMMU2 and SMMU3. see if this is a Cavium SMMU, if so + * set asid and vmid base such that each SMMU gets unique + * asid/vmid space. + */ + if (!strcasecmp(of_id->compatible, "cavium,smmu-v2")) { + /* VMID16 must be present on Cavium SMMUv2*/ + if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) + goto out_free_irqs; + smmu->cavium_smmu_id = cavium_smmu_count; + cavium_smmu_count++; + smmu->cavium_id_base = + (smmu->cavium_smmu_id * ARM_SMMU_MAX_CBS); + } + INIT_LIST_HEAD(&smmu->list); spin_lock(&arm_smmu_devices_lock); list_add(&smmu->list, &arm_smmu_devices);