From patchwork Tue Mar 1 06:35:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 8462361 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B4CBA9F314 for ; Tue, 1 Mar 2016 06:39:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B835D202D1 for ; Tue, 1 Mar 2016 06:39:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C20520306 for ; Tue, 1 Mar 2016 06:39:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aadwT-0002tr-Go; Tue, 01 Mar 2016 06:37:57 +0000 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aadw2-0002b8-MP for linux-arm-kernel@lists.infradead.org; Tue, 01 Mar 2016 06:37:32 +0000 Received: by mail-pf0-x233.google.com with SMTP id l6so9613537pfl.3 for ; Mon, 29 Feb 2016 22:37:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=YRezMspNWMD3Gr1pSqNlrck4cgzlG+ZrxpyLCg8Bw8Rz8FO0nxxuI8z1X6olErBEtB iQWTDOD62guvYTK2Nx/RmrHF4QjFbbV9GeRZWw4q0taj0oC7Wi7iu19QNjTheBoTofnY qBgd+7rrb4KCK7VIPtI7u4JMGMC6vzqiadSWQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=cl2ZA/Loi4aKhT1hnifBwzjRx6TMlUmQi5uz2I/BvhTrHA+HIX8ImjoPDWAtGkO0zJ SXSRcvhrimEVLdNzBV4T2UAUFyYlRo7fYVaVEeCjosdW/P+Aqjj3L8QnjSItAdtjNID5 /ReucFUNlY3BIha+H25GNo8D3G0D+v07LuiOi4YXsYntatkt0PQmEISCiOMRQCHGdYpw uIPf+VxIzG7ATF1TJ+My3aAqxBR5UYDnK0IH55XdMJGLqYnaLau5zGY8npWJVxOrFIa3 vkDvwCH+6U81jDWlUmvmSy5dclt3EPvJhTCE96+Aq5V2dp9wvvx5oh1aactTYG3TcKOr zLnQ== X-Gm-Message-State: AD7BkJLG2ToAA9uh3z51+qNFY4RkBkeSNpbn8gULqRMxkHI07LFMYb5mjeJcmcYMp5SvJ9QW X-Received: by 10.98.9.27 with SMTP id e27mr28130029pfd.59.1456814229918; Mon, 29 Feb 2016 22:37:09 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id y21sm26485895pfa.85.2016.02.29.22.37.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 Feb 2016 22:37:08 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Subject: [PATCH V4 3/4] coresight-stm: Bindings for System Trace Macrocell Date: Tue, 1 Mar 2016 14:35:08 +0800 Message-Id: <1456814109-21311-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456814109-21311-1-git-send-email-zhang.chunyan@linaro.org> References: <1456814109-21311-1-git-send-email-zhang.chunyan@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160229_223730_924130_1535BC67 X-CRM114-Status: GOOD ( 10.96 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, Michael.Williams@arm.com, linux-doc@vger.kernel.org, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, tor@ti.com, mike.leach@arm.com, linux-api@vger.kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.