From patchwork Tue Mar 1 21:15:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 8470561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9E803C0553 for ; Tue, 1 Mar 2016 21:21:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9971620304 for ; Tue, 1 Mar 2016 21:21:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 865052010E for ; Tue, 1 Mar 2016 21:21:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aarhW-0003ZP-Jv; Tue, 01 Mar 2016 21:19:26 +0000 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aarep-0000u7-56 for linux-arm-kernel@lists.infradead.org; Tue, 01 Mar 2016 21:16:46 +0000 Received: by mail-pf0-x235.google.com with SMTP id l6so22279530pfl.3 for ; Tue, 01 Mar 2016 13:16:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3OJLGmomUVzoNhG3k66l49voyoWKM6mQ/5ijMVJj2Ao=; b=GYJ6/bSwxAhqDJv/YOHWIuEUn0G1bnV73eTnZCw01FBJ6uDStMoeQ5LbyrhkMPfaH9 LMdLCWXOMvawBUF5tTQ3GbsTrKE4A0Mr5qBrO3BzQTYCw4jE3uPtXb3JecnPHMmiCI4f gh+MLoQyP7+u4WgFzGr6hCpAoCuJm4wA/6AWM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3OJLGmomUVzoNhG3k66l49voyoWKM6mQ/5ijMVJj2Ao=; b=WIJKecmFScF+E5EcV2VrvnKFbwQDaFSyIMBWTxJYPBzwvB70vil6MHLIYfHmRekbH6 SFDjvJzWsQaKzehBGKJeGbg1fxaBnhQDEMrvxPPlxKO1DI2caP8ie/asR7G7HHp7OU+T CFo7Ir9/drGKB3nIHXeTHaVt3XCwMVGFS9H1OCQk9FdvqsXdWGuq1bjFst0YMgbCiKcO 8MaKOTPX4DZXkVCX/FDvu8fVebBlODGTOfEEeyd4N1OzlLUXhGmsu57fjkqLmYQk4YAB YEDmFRT3nV1zyktnANT8kRaK6Mr7NmKmN1tulaU3e9RkpR/G1aPFId7n3FXZLhXf0ms9 ScMA== X-Gm-Message-State: AD7BkJItBEHQPYwCYQBOeyjn2xdZM2S4GsV/0mPm17alXmBV0dqVDAXVCfQ5bQVHmUwvS8kk X-Received: by 10.98.70.211 with SMTP id o80mr33042275pfi.124.1456866981425; Tue, 01 Mar 2016 13:16:21 -0800 (PST) Received: from ubuntu.localdomain (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id kw10sm47749328pab.0.2016.03.01.13.16.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Mar 2016 13:16:20 -0800 (PST) From: Lina Iyer To: ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC v3 08/12] Documentation / cpu_domains: Describe CPU PM domains setup and governor Date: Tue, 1 Mar 2016 14:15:27 -0700 Message-Id: <1456866931-37851-10-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1456866931-37851-1-git-send-email-lina.iyer@linaro.org> References: <1456866931-37851-1-git-send-email-lina.iyer@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160301_131639_621456_7F8A130D X-CRM114-Status: GOOD ( 21.66 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: k.kozlowski@samsung.com, lorenzo.pieralisi@arm.com, ahaslam@baylibre.com, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, msivasub@codeaurora.org, geert@linux-m68k.org, Lina Iyer , agross@codeaurora.org, mtitinger@baylibre.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A generic CPU PM domain functionality is provided by drivers/base/power/cpu_domains.c. This document describes the generic usecase of CPU's PM domains, the setup of such domains and a CPU specific genpd governor. Signed-off-by: Lina Iyer --- Documentation/power/cpu_domains.txt | 79 +++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/power/cpu_domains.txt diff --git a/Documentation/power/cpu_domains.txt b/Documentation/power/cpu_domains.txt new file mode 100644 index 0000000..bd99e92 --- /dev/null +++ b/Documentation/power/cpu_domains.txt @@ -0,0 +1,79 @@ +CPU PM domains +============== + +Newer CPUs are grouped in SoCs as clusters. A cluster in addition to the CPUs +may have caches, floating point units and other architecture specific power +controller that share resources when any of the CPUs are active. When the CPUs +are in idle, some of these cluster components may also idle. A cluster may +also be nested inside another cluster that provides common coherency +interfaces to share data between the clusters. The organization of such +clusters and CPU may be descibed in DT, since they are SoC specific. + +CPUIdle framework enables the CPUs to determine the sleep time and enter low +power state to save power during periods of idle. CPUs in a cluster may enter +and exit idle state independently of each other. During the time when all the +CPUs are in idle state, the cluster may safely put some of the shared +resources in their idle state. The time between the last CPU to enter idle and +the first CPU to wake up is the time available for the cluster to enter its +idle state. + +When SoCs power down the CPU during cpuidle, they generally have supplemental +hardware that can handshake with the CPU with a signal that indicates that the +CPU has stopped execution. The hardware is also responsible for warm booting +the CPU on receiving an interrupt. In a cluster architecture, common resources +that are shared by a cluster may also be powered down by an external +microcontroller or a processor. The microcontroller may be programmed in +advance to put the hardware blocks in a low power state, when the last active +CPU sends the idle signal. When the signal is received, the microcontroller +may trigger the hardware blocks to enter their low power state. When an +interrupt to wakeup the processor is received, the microcontroller is +responsible for bringing up the hardware blocks to its active state, before +waking up the CPU. The timelines for such operations should be in the +acceptable range for for CPU idle to get power benefits. + +CPU PM Domain Setup +------------------- + +PM domains are represented in the DT as domain consumers and providers. A +device may have a domain provider and a domain provider may support multiple +domain consumers. Domains like clusters, may also be nested inside one +another. A domain that has no active consumer, may be powered off and any +resuming consumer would trigger the domain back to active. Parent domains may +be powered off when the child domains are powered off. The CPU cluster can be +fashioned as a PM domain. When the CPU devices are powered off, the PM domain +may be powered off. + +Device idle is reference counted by runtime PM. When there is no active need +for the device, runtime PM invokes callbacks to suspend the parent domain. +Generic PM domain (genpd) handles the hierarchy of devices, domains and the +reference counting of objects leading to last man down and first man up in the +domain. The CPU domains helper functions defines PM domains for each CPU +cluster and attaches the CPU devices to the respective PM domains. + +Platform drivers may use the following API to register their CPU PM domains. + +of_setup_cpu_pd() - +Provides a single step registration of the CPU PM domain and attach CPUs to +the genpd. Platform drivers may additionally register callbacks for power_on +and power_off operations for the PM domain. + +of_setup_cpu_pd_single() - +Define PM domain for a single CPU and attach the CPU to its domain. + + +CPU PM Domain governor +---------------------- + +CPUs have a unique ability to determine their next wakeup. CPUs may wake up +for known timer interrupts and unknown interrupts from idle. Prediction +algorithms and heuristic based algorithms like the Menu governor for cpuidle +can determine the next wakeup of the CPU. However, determining the wakeup +across a group of CPUs is a tough problem to solve. + +A simplistic approach would be to resort to known wakeups of the CPUs in +determining the next wakeup of any CPU in the cluster. The CPU PM domain +governor does just that. By looking into the tick device of the CPUs, the +governor can determine the sleep time between the last CPU and the first +scheduled wakeup of any CPU in that domain. This combined with the PM QoS +requirement for CPU_DMA_LATENCY can be used to determine the deepest possible +idle state of the CPU domain.