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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id kw10sm47749328pab.0.2016.03.01.13.16.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Mar 2016 13:16:12 -0800 (PST) From: Lina Iyer To: ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC v3 05/12] timer: Export next wake up of a CPU Date: Tue, 1 Mar 2016 14:15:24 -0700 Message-Id: <1456866931-37851-7-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1456866931-37851-1-git-send-email-lina.iyer@linaro.org> References: <1456866931-37851-1-git-send-email-lina.iyer@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160301_131634_693165_A2005297 X-CRM114-Status: GOOD ( 13.43 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: k.kozlowski@samsung.com, lorenzo.pieralisi@arm.com, ahaslam@baylibre.com, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, msivasub@codeaurora.org, geert@linux-m68k.org, Lina Iyer , agross@codeaurora.org, Thomas Gleixner , mtitinger@baylibre.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Knowing the sleep length of the CPU is useful for the power state determination on idle. However, when the common sleep time between multiple CPUs is needed, the sleep length of a CPU is not useful. By reading the next wake up event of a CPU, governors can determine the first CPU to wake up (due to timer) amongst a cluster of CPUs and the sleep time available between the last CPU to idle and the first CPU to resume. This information is useful to determine if the caches and other common hardware blocks can also be put in idle during this common period of inactivity. Cc: Thomas Gleixner Signed-off-by: Lina Iyer --- include/linux/tick.h | 10 ++++++++++ kernel/time/tick-sched.c | 13 +++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/linux/tick.h b/include/linux/tick.h index 97fd4e5..b8a2e06 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -104,6 +104,7 @@ extern void tick_nohz_idle_enter(void); extern void tick_nohz_idle_exit(void); extern void tick_nohz_irq_exit(void); extern ktime_t tick_nohz_get_sleep_length(void); +extern ktime_t tick_nohz_get_next_wakeup(int cpu); extern u64 get_cpu_idle_time_us(int cpu, u64 *last_update_time); extern u64 get_cpu_iowait_time_us(int cpu, u64 *last_update_time); #else /* !CONFIG_NO_HZ_COMMON */ @@ -118,6 +119,15 @@ static inline ktime_t tick_nohz_get_sleep_length(void) return len; } + +static inline ktime_t tick_nohz_get_next_wakeup(int cpu) +{ + ktime_t len = { .tv64 = NSEC_PER_SEC/HZ }; + + /* Next wake up is the tick period, assume it starts now */ + return ktime_add(len, ktime_get()); +} + static inline u64 get_cpu_idle_time_us(int cpu, u64 *unused) { return -1; } static inline u64 get_cpu_iowait_time_us(int cpu, u64 *unused) { return -1; } #endif /* !CONFIG_NO_HZ_COMMON */ diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 0b17424..f0ddaec 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -888,6 +888,19 @@ ktime_t tick_nohz_get_sleep_length(void) return ts->sleep_length; } +/** + * tick_nohz_get_next_wakeup - return the next wake up of the CPU + * + * Called with interrupts disabled on the cpu + */ +ktime_t tick_nohz_get_next_wakeup(int cpu) +{ + struct clock_event_device *dev = + per_cpu(tick_cpu_device.evtdev, cpu); + + return dev->next_event; +} + static void tick_nohz_account_idle_ticks(struct tick_sched *ts) { #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE