From patchwork Thu Mar 3 11:39:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8491591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9BE4BC0553 for ; Thu, 3 Mar 2016 11:44:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 63B7620254 for ; Thu, 3 Mar 2016 11:44:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A32D201EF for ; Thu, 3 Mar 2016 11:44:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRdW-0007Kl-Em; Thu, 03 Mar 2016 11:41:42 +0000 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRci-0006yY-SM for linux-arm-kernel@lists.infradead.org; Thu, 03 Mar 2016 11:40:55 +0000 Received: by mail-wm0-x230.google.com with SMTP id p65so30670320wmp.1 for ; Thu, 03 Mar 2016 03:40:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xWm2bueyEVTz2BxSJccJWRt9bxVo4SgFl9BfkPVXnCI=; b=rI2NUYJb9YIHKmVP11InHXF46G4FNJwJ1fWCp43g/A8pGO2S7QmtDL0oyRMa5rJPbW yOkUNFOfW0h4jX/Mo28m+HPss7KTLNN2E0fECga34309xg7/En/sa6frnC6z6Ek6uS+T J0RwL0kyOdakPsqkKuk1aPC3gwxwOnED4F7+Le+cGUzo3bSQC43ke9qwhTdmbObLMngs tpPZQL03XjwpusP/PeymS/HJ0jcAP8OFQy2R70iWoz4VYU53bLf5bRhyv5P+YDsnKF48 QeRJ1gG4am4wCqLlnoww49GLeFMEePjyD3Ychz8OvktfIVTbUV25ca6hPZBXULgpvBer vkAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xWm2bueyEVTz2BxSJccJWRt9bxVo4SgFl9BfkPVXnCI=; b=RmXfM+5X6K1ClH+F3I2+OTeRWH7fot3uTbjPa35/psckfOcuc/huFJS8u2OajkjHYK zWgzFF3xuHDl3XfmoH34/PVArw0Z9jVYdhFW5JgpyU8KTdsUoSIbtx5qCE3Bb/Vuo0kd TKtA9ttQr67jHzfX7ng7GRtBHHte3SS040y7JzbBGssPJV0W5oMzx31cJ8brAwH7Wac6 1Q0JHhE5JjSAPey5jVJayH0Ud0kyhlTLH7B2cyo4mySAQKM6+TnE5Ph5qVpbvul440N1 fdcBIPL8twVY1cD7NIQTCCV5EEoAa8cgo2bQAsvsIDEoE01nCsqhSMXbKT/14AVPQdlx BfOA== X-Gm-Message-State: AD7BkJKUestHK8P2VnBy+H9jVxJEv5WUzA9uT3d6KNsk7JCE7y/L0gpJSoLwNfcsyFvb7Phn X-Received: by 10.194.90.77 with SMTP id bu13mr2437635wjb.60.1457005233252; Thu, 03 Mar 2016 03:40:33 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j18sm8559725wmd.2.2016.03.03.03.40.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Mar 2016 03:40:32 -0800 (PST) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, daniel.lezcano@linaro.org, tglx@linutronix.de Subject: [PATCH 04/17] clocksource: Add PLX Technology RPS Timer Date: Thu, 3 Mar 2016 12:39:57 +0100 Message-Id: <1457005210-18485-5-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160303_034053_308440_0DF17985 X-CRM114-Status: GOOD ( 20.95 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ma Haijun , Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add clocksource and clockevent driver from dual RPS timer. CC: Ma Haijun Signed-off-by: Neil Armstrong --- drivers/clocksource/Kconfig | 6 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rps.c | 249 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 drivers/clocksource/timer-rps.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 33db740..f79bc0f 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -276,6 +276,12 @@ config VF_PIT_TIMER help Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. +config CLKSRC_RPS_TIMER + bool + select CLKSRC_MMIO + help + This enables support for the PLX Tech OXNAS RPS timers. + config SYS_SUPPORTS_SH_CMT bool diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dc2b899..120bc09 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o +obj-$(CONFIG_CLKSRC_RPS_TIMER) += timer-rps.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o diff --git a/drivers/clocksource/timer-rps.c b/drivers/clocksource/timer-rps.c new file mode 100644 index 0000000..79621b8 --- /dev/null +++ b/drivers/clocksource/timer-rps.c @@ -0,0 +1,249 @@ +/* + * drivers/clocksource/timer-rps.c + * + * Copyright (C) 2009 Oxford Semiconductor Ltd + * Copyright (C) 2013 Ma Haijun + * Copyright (C) 2016 Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TIMER1 as tick + * TIMER2 as clocksource + */ + +enum { + TIMER_LOAD = 0, + TIMER_CURR = 4, + TIMER_CTRL = 8, + TIMER_CLRINT = 0xC, + + TIMER_BITS = 24, + + TIMER_MAX_VAL = (1 << TIMER_BITS) - 1, + + TIMER_PERIODIC = (1 << 6), + TIMER_ENABLE = (1 << 7), + + TIMER_DIV1 = (0 << 2), + TIMER_DIV16 = (1 << 2), + TIMER_DIV256 = (2 << 2), + + TIMER1_OFFSET = 0, + TIMER2_OFFSET = 0x20, +}; + +/* Clockevent */ + +static unsigned long timer_period = HZ; +static unsigned timer_prescaler = 1; +static void __iomem *timer_base; + +static irqreturn_t rps_timer_irq(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + iowrite32(0, timer_base + TIMER_CLRINT); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void rps_timer_config(unsigned long period, unsigned periodic) +{ + uint32_t cfg = 0; + + if (period) + cfg |= TIMER_ENABLE; + + if (periodic) + cfg |= TIMER_PERIODIC; + + switch (timer_prescaler) { + case 1: + cfg |= TIMER_DIV1; + break; + case 16: + cfg |= TIMER_DIV16; + break; + case 256: + cfg |= TIMER_DIV256; + break; + } + + iowrite32(period, timer_base + TIMER_LOAD); + iowrite32(cfg, timer_base + TIMER_CTRL); +} + +static int rps_timer_shutdown(struct clock_event_device *evt) +{ + if (!clockevent_state_periodic(evt)) + return 0; + + rps_timer_config(0, 0); + + return 0; +} + +static int rps_timer_set_periodic(struct clock_event_device *evt) +{ + rps_timer_config(timer_period, 1); + + return 0; +} + +static int rps_timer_set_oneshot(struct clock_event_device *evt) +{ + rps_timer_config(timer_period, 0); + + return 0; +} + +static int rps_timer_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + rps_timer_config(delta, 0); + + return 0; +} + +static struct clock_event_device rps_clockevent = { + .name = "rps", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .tick_resume = rps_timer_shutdown, + .set_state_shutdown = rps_timer_shutdown, + .set_state_periodic = rps_timer_set_periodic, + .set_state_oneshot = rps_timer_set_oneshot, + .set_next_event = rps_timer_next_event, + .rating = 200, +}; + +static void __init rps_clockevent_init(void __iomem *base, ulong ref_rate, + int irq) +{ + timer_base = base; + + /* Start with prescaler 1 */ + timer_prescaler = 1; + timer_period = DIV_ROUND_UP(ref_rate, HZ); + + if (timer_period > TIMER_MAX_VAL) { + timer_prescaler = 16; + timer_period = DIV_ROUND_UP(ref_rate / timer_prescaler, HZ); + } + if (timer_period > TIMER_MAX_VAL) { + timer_prescaler = 256; + timer_period = DIV_ROUND_UP(ref_rate / timer_prescaler, HZ); + } + + rps_clockevent.cpumask = cpu_possible_mask; + rps_clockevent.irq = irq; + clockevents_config_and_register(&rps_clockevent, + ref_rate / timer_prescaler, + 1, + TIMER_MAX_VAL); + + pr_info("rps: Registered clock event rate %luHz prescaler %d period %lu\n", + ref_rate, + timer_prescaler, + timer_period); +} + +/* Clocksource */ + +static void __iomem *timer_curr; + +static u64 notrace rps_read_sched_clock(void) +{ + return ~readl_relaxed(timer_curr); +} + +static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate) +{ + int ret; + ulong clock_rate; + /* use prescale 16 */ + clock_rate = ref_rate / 16; + + iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD); + iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, + base + TIMER_CTRL); + + timer_curr = base + TIMER_CURR; + sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate); + ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer", + clock_rate, 250, TIMER_BITS, + clocksource_mmio_readl_down); + if (ret) + panic("can't register clocksource\n"); + + pr_info("rps: Registered clocksource rate %luHz\n", clock_rate); +} + +static struct irqaction rps_timer_irqaction = { + .name = "rps_timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = rps_timer_irq, + .dev_id = &rps_clockevent, +}; + +static void __init rps_timer_init(struct device_node *np) +{ + struct clk *refclk; + unsigned long ref_rate; + void __iomem *base; + int irq, ret; + + refclk = of_clk_get(np, 0); + + if (IS_ERR(refclk) || clk_prepare_enable(refclk)) + panic("rps_timer_init: failed to get refclk\n"); + ref_rate = clk_get_rate(refclk); + + base = of_iomap(np, 0); + if (!base) + panic("rps_timer_init: failed to map io\n"); + + irq = irq_of_parse_and_map(np, 0); + if (irq < 0) + panic("rps_timer_init: failed to parse IRQ\n"); + + /* Disable timers */ + iowrite32(0, base + TIMER1_OFFSET + TIMER_CTRL); + iowrite32(0, base + TIMER2_OFFSET + TIMER_CTRL); + iowrite32(0, base + TIMER1_OFFSET + TIMER_LOAD); + iowrite32(0, base + TIMER2_OFFSET + TIMER_LOAD); + iowrite32(0, base + TIMER1_OFFSET + TIMER_CLRINT); + iowrite32(0, base + TIMER2_OFFSET + TIMER_CLRINT); + + rps_clocksource_init(base + TIMER2_OFFSET, ref_rate); + rps_clockevent_init(base + TIMER1_OFFSET, ref_rate, irq); + + ret = setup_irq(irq, &rps_timer_irqaction); + if (ret) + panic("rps_timer_init: failed to request irq\n"); +} + +CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init);