From patchwork Thu Mar 3 11:40:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8491771 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 356809F2F0 for ; Thu, 3 Mar 2016 11:48:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 12EA82026C for ; Thu, 3 Mar 2016 11:47:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B7B2D2011B for ; Thu, 3 Mar 2016 11:47:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRgl-0001hQ-Fy; Thu, 03 Mar 2016 11:45:03 +0000 Received: from mail-wm0-x22a.google.com ([2a00:1450:400c:c09::22a]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRco-0006yg-FP for linux-arm-kernel@lists.infradead.org; Thu, 03 Mar 2016 11:41:04 +0000 Received: by mail-wm0-x22a.google.com with SMTP id p65so27837764wmp.0 for ; Thu, 03 Mar 2016 03:40:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=umsAxPfy9is2HqmeQnf6mZ1d4qtRDPhQN5FHvmOFQzw=; b=BMnhsbthtrFfXWKDlkut/LvE8PhZVZcZi6SPJlU3Jej7WEUTgTbmVL8H5SbXUN8dFH 6L6GtFoExbOyuHDfVusEGxJ+6W7LqJ2dsLYTBJNRun//nMRr21MkRujJjlMnM/PPPcDx mPkUYI5wBLY5A6kqBUlUQkQHH065Ai4e+/jCwss70khmriPm+xKO3O6e2ko5aeVadlv0 FLUO05ollfRsesTXqDnWOyg7lBvgAvPI4iU25NuCetgD0rVOW4MiIC50nZ/Isrmh3wsB vV84zSIeryVZRaV5AqZeF9bYb/eZOPPLvei86QzEY1vRjnh8TY8+BjRa/dLkvtUCOtf/ YxDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=umsAxPfy9is2HqmeQnf6mZ1d4qtRDPhQN5FHvmOFQzw=; b=gdpgMYYdKsU6yOy9IF0FrkLQ7e+tS+NrITYfx4GgdXu6NT+Haix80WRu2cj7J6+7/7 3yetal7FZ4spOkvSPVggPnothq+6IwIueXttiZ5DUCz7sE7XzTcQfXyMv+9wNvO78sbt 0To/T48KLYVefCUs4Om0QxgeP1w/Q6J+o+T5WnsItlacbpPRSLljijkBo3ZQiSARAK/l qk2dfVHflgVSWrSPALdd6p9/qa8GB6KjmvKMqA7p5PC0IuE6Q/hyTDEP5zJQ1sL+OhbP QXc4Y/khWpNXkbrR+jclc1Q1ofp3F7JLphO1/Oi77WXudzpBDN2qHS+SdeMQe7KTfGm6 T4ig== X-Gm-Message-State: AD7BkJKfmPOkhetPgCM/JRQZ/lQJvCQJCIeCc5FXH4p1SE6WShfktnaBm5uGaFCG2hNyC++J X-Received: by 10.28.61.215 with SMTP id k206mr5094482wma.38.1457005236925; Thu, 03 Mar 2016 03:40:36 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j18sm8559725wmd.2.2016.03.03.03.40.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Mar 2016 03:40:36 -0800 (PST) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 08/17] clk: Add PLX Technology OXNAS Standard Clocks Date: Thu, 3 Mar 2016 12:40:01 +0100 Message-Id: <1457005210-18485-9-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160303_034058_967347_1E8B242F X-CRM114-Status: GOOD ( 20.13 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PLX Technology OXNAS SoC Family Standard Clocks support. Signed-off-by: Neil Armstrong --- drivers/clk/Kconfig | 6 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-oxnas.c | 159 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/clk/clk-oxnas.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index eca8e01..b75ef5c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -192,6 +192,12 @@ config COMMON_CLK_PXA ---help--- Sypport for the Marvell PXA SoC. +config COMMON_CLK_OXNAS + def_bool COMMON_CLK + select MFD_SYSCON + ---help--- + Sypport for the OXNAS SoC Family clocks. + config COMMON_CLK_CDCE706 tristate "Clock driver for TI CDCE706 clock synthesizer" depends on I2C diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index bae4be6..a5d45d8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o +obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c new file mode 100644 index 0000000..c4b903f --- /dev/null +++ b/drivers/clk/clk-oxnas.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2010 Broadcom + * Copyright (C) 2012 Stephen Warren + * Copyright (C) 2016 Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Standard regmap gate clocks */ +struct clk_std { + struct clk_hw hw; + signed char bit; + struct regmap *regmap; +}; + +/* Regmap offsets */ +#define CLK_STAT_REGOFFSET 0x24 +#define CLK_SET_REGOFFSET 0x2c +#define CLK_CLR_REGOFFSET 0x30 + +#define NUM_STD_CLKS 10 +#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) + +static int std_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_std *std = to_stdclk(hw); + int ret; + unsigned int val; + + ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val); + if (ret < 0) + return ret; + + return val & BIT(std->bit); +} + +static int std_clk_enable(struct clk_hw *hw) +{ + struct clk_std *std = to_stdclk(hw); + + regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit)); + + return 0; +} + +static void std_clk_disable(struct clk_hw *hw) +{ + struct clk_std *std = to_stdclk(hw); + + regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit)); +} + +static struct clk_ops std_clk_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, + .is_enabled = std_clk_is_enabled, +}; + +static const char *const std_clk_parents[] = { + "oscillator", +}; + +static const char *const eth_parents[] = { + "gmacclk", +}; + +#define DECLARE_STD_CLKP(__clk, __bit, __parent) \ +static struct clk_init_data clk_##__clk##_init = { \ + .name = __stringify(__clk), \ + .ops = &std_clk_ops, \ + .parent_names = __parent, \ + .num_parents = ARRAY_SIZE(__parent), \ +}; \ + \ +static struct clk_std clk_##__clk = { \ + .bit = __bit, \ + .hw = { \ + .init = &clk_##__clk##_init, \ + }, \ +} + +#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \ + std_clk_parents) + +DECLARE_STD_CLK(leon, 0); +DECLARE_STD_CLK(dma_sgdma, 1); +DECLARE_STD_CLK(cipher, 2); +/* DECLARE_STD_CLK(sd, 3); - Do not touch DDR clock */ +DECLARE_STD_CLK(sata, 4); +DECLARE_STD_CLK(audio, 5); +DECLARE_STD_CLK(usbmph, 6); +DECLARE_STD_CLKP(etha, 7, eth_parents); +DECLARE_STD_CLK(pciea, 8); +DECLARE_STD_CLK(nand, 9); + +static struct clk_hw *std_clk_hw_tbl[] = { + &clk_leon.hw, + &clk_dma_sgdma.hw, + &clk_cipher.hw, + &clk_sata.hw, + &clk_audio.hw, + &clk_usbmph.hw, + &clk_etha.hw, + &clk_pciea.hw, + &clk_nand.hw, +}; + +static struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)]; + +static struct clk_onecell_data std_clk_data; + +static void __init oxnas_init_stdclk(struct device_node *np) +{ + int i; + struct regmap *regmap = syscon_node_to_regmap(of_get_parent(np)); + + if (!regmap) + panic("failed to have parent regmap\n"); + + for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) { + struct clk_std *std = container_of(std_clk_hw_tbl[i], + struct clk_std, hw); + + if (WARN_ON(!std)) + return; + std->regmap = regmap; + + std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]); + if (WARN_ON(IS_ERR(std_clk_tbl[i]))) + return; + } + + std_clk_data.clks = std_clk_tbl; + std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl); + + of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data); +} +CLK_OF_DECLARE(oxnas_pllstd, "plxtech,ox810se-stdclk", oxnas_init_stdclk);