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Fri, 4 Mar 2016 03:44:11 +0000 From: Tirumalesh Chalamarla To: , , Subject: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704 Date: Thu, 3 Mar 2016 19:44:03 -0800 Message-ID: <1457063043-10623-1-git-send-email-tchalamarla@caviumnetworks.com> X-Mailer: git-send-email 2.1.0 MIME-Version: 1.0 X-Originating-IP: [64.2.3.194] X-ClientProxiedBy: CY1PR21CA0050.namprd21.prod.outlook.com (25.163.250.146) To SN1PR0701MB1789.namprd07.prod.outlook.com (25.162.100.143) X-Microsoft-Exchange-Diagnostics: 1; SN1PR0701MB1789; 2:MiS+BmkHg5IwkFEhqVhWrWov1ijJ0iGyhjz4t2NXnYR70gFYMoiVoupuy/jshV9YIKhhe9bmLHgHOwULyh2FAVvZ2d8jqTIWxAep3TSExIBeErKg7CjYcaQ9xLJYNIV+XKxF98CBv4307jcumGAaCg==; 3:Z7ZTtDrzbHhaa4A+Y5Pcr5S0BN46cMIgA01UEDeYFikHjOwfnS443Y1lvgSc975M0ECgJbpBgSrswZAmE29B50ixiloluT29FxZTgWG0n2O51ufGm6f5bkCfu1Hs6JT8; 25:d2l2ZVaAi1IfvaANEJji+JnYUvpdxmFI/5DRCX3Y82PI6skXf+DQsB9CjDqLhi0vnetuc9aRyJlkboHwTpj+0svEHAVwkY5Th2Ckglw8Ej10rVD6N151Pn2KNt7NKa5IZahjTixEzxicgAdn6R1OrFFRDGT7X1OyIyEdA+hSi6dDwT7SmvWu2quMccKWYXo7vPgKi6pPgIzM2QHnPpNRQwXj0a45P6OygBjieQ/qmxxs+WBpOR4uOXEBPNwps6VOPJKmBv8CqISPIoMxOIqC+Xv83QYFii1lLDHXQY3Jae77Bpox3NTfPWQVmiJwVgSxgHYWl2C03Ze/d7qx9Jd1JQ== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SN1PR0701MB1789; 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specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3. This patch make sures ASID and VMID space is unique across cavium SMMUv2. changes from V3: - Removed redundent variable. changes from V2: - removed *_base from DT, and replaced with compatible string changes from V1: - rebased on top of 16 bit VMID patch - removed redundent options from DT - insted of transform, DT now supplies starting ASID/VMID Signed-off-by: Tirumalesh Chalamarla Signed-off-by: Akula Geethasowjanya --- Documentation/arm64/silicon-errata.txt | 1 + .../devicetree/bindings/iommu/arm,smmu.txt | 1 + drivers/iommu/arm-smmu.c | 43 ++++++++++++++++------ 3 files changed, 34 insertions(+), 11 deletions(-) -- 2.1.0 diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 58b71dd..3747a4b 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX SMMUv2 | #27704 | N/A | diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 7180745..19fe6f2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -16,6 +16,7 @@ conditions. "arm,mmu-400" "arm,mmu-401" "arm,mmu-500" + "cavium,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 247a469..bfe38f3 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -326,6 +326,11 @@ struct arm_smmu_device { struct list_head list; struct rb_root masters; + /* + *The following fields are specific to Cavium, Thunder + */ + u32 cavium_id_base; + }; struct arm_smmu_cfg { @@ -335,8 +340,8 @@ struct arm_smmu_cfg { }; #define INVALID_IRPTNDX 0xff -#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) -#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) +#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx) +#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1) enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, @@ -364,6 +369,8 @@ struct arm_smmu_option_prop { const char *prop; }; +static u32 cavium_smmu_context_count; + static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, { 0, NULL}, @@ -575,11 +582,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) if (stage1) { base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); - writel_relaxed(ARM_SMMU_CB_ASID(cfg), + writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg), base + ARM_SMMU_CB_S1_TLBIASID); } else { base = ARM_SMMU_GR0(smmu); - writel_relaxed(ARM_SMMU_CB_VMID(cfg), + writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), base + ARM_SMMU_GR0_TLBIVMID); } @@ -601,7 +608,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) { iova &= ~12UL; - iova |= ARM_SMMU_CB_ASID(cfg); + iova |= ARM_SMMU_CB_ASID(smmu, cfg); do { writel_relaxed(iova, reg); iova += granule; @@ -609,7 +616,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, #ifdef CONFIG_64BIT } else { iova >>= 12; - iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48; + iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48; do { writeq_relaxed(iova, reg); iova += granule >> 12; @@ -629,7 +636,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, #endif } else { reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; - writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); + writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg); } } @@ -738,7 +745,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, #endif /* if 16bit VMID supported set VMID in CBA2R */ if (smmu->features & ARM_SMMU_FEAT_VMID16) - reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT; + reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT; writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); } @@ -757,7 +764,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { /*16 bit VMID is not supported set 8 bit VMID here */ - reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; + reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT; } writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); @@ -765,11 +772,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, if (stage1) { reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; - reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; + reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0); reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; - reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; + reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1); } else { reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; @@ -1717,6 +1724,7 @@ static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, + { .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); @@ -1829,6 +1837,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev) INIT_LIST_HEAD(&smmu->list); spin_lock(&arm_smmu_devices_lock); + + /* + * Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID + * namespaces; specifically within a given node SMMU0 and SMMU1 share, + * as does SMMU2 and SMMU3. see if this is a Cavium SMMU, if so + * set asid and vmid base such that each SMMU gets unique + * asid/vmid space. + */ + if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) { + smmu->cavium_id_base = cavium_smmu_context_count; + cavium_smmu_context_count += smmu->num_context_banks; + } + list_add(&smmu->list, &arm_smmu_devices); spin_unlock(&arm_smmu_devices_lock);