From patchwork Fri Mar 4 12:57:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 8503611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 346D99F7CA for ; Fri, 4 Mar 2016 13:02:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2D404201FE for ; Fri, 4 Mar 2016 13:02:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D9E7201CD for ; Fri, 4 Mar 2016 13:02:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1abpJr-0003ka-1w; Fri, 04 Mar 2016 12:58:59 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1abpJL-0003d9-Mr for linux-arm-kernel@lists.infradead.org; Fri, 04 Mar 2016 12:58:31 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id BBA0D3FA; Fri, 4 Mar 2016 13:58:04 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-1129-172.w92-156.abo.wanadoo.fr [92.156.51.172]) by mail.free-electrons.com (Postfix) with ESMTPSA id 85695228; Fri, 4 Mar 2016 13:58:04 +0100 (CET) From: Thomas Petazzoni To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH v3 3/3] clk: mvebu: new driver for Armada AP806 system controller Date: Fri, 4 Mar 2016 13:57:55 +0100 Message-Id: <1457096275-7581-4-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1457096275-7581-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1457096275-7581-1-git-send-email-thomas.petazzoni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160304_045828_182304_025935EF X-CRM114-Status: GOOD ( 19.53 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lior Amsalem , Andrew Lunn , Yehuda Yitschak , Jason Cooper , Pawel Moll , devicetree@vger.kernel.org, Ian Campbell , Nadav Haklai , Rob Herring , Neta Zur Hershkovits , Kumar Gala , Gregory Clement , Mark Rutland , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Armada AP806 system controller, amongst other things, provides a number of clocks for the platform: the CPU cluster clocks, whose frequencies are found by reading the Sample At Reset register, one fixed clock, and another clock derived from the fixed clock, which is the one used by most peripherals in AP806. The AP806 is one of the two core HW blocks used in the Marvell 7K/8K SoCs. Signed-off-by: Thomas Petazzoni --- drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/ap806-system-controller.c | 106 ++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 drivers/clk/mvebu/ap806-system-controller.c diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig index eaee8f0..bf7ae00 100644 --- a/drivers/clk/mvebu/Kconfig +++ b/drivers/clk/mvebu/Kconfig @@ -29,6 +29,9 @@ config ARMADA_XP_CLK select MVEBU_CLK_COMMON select MVEBU_CLK_CPU +config ARMADA_AP806_SYSCON + bool + config DOVE_CLK bool select MVEBU_CLK_COMMON diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index 8866115..f4aa481 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o +obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o obj-$(CONFIG_ORION_CLK) += orion.o diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c new file mode 100644 index 0000000..c33c209 --- /dev/null +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -0,0 +1,106 @@ +/* + * Marvell Armada AP806 System Controller + * + * Copyright (C) 2016 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "ap806-system-controller: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#define AP806_SAR_REG 0x400 +#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f + +#define AP806_CLK_NUM 4 + +static struct clk *ap806_clks[AP806_CLK_NUM]; + +static struct clk_onecell_data ap806_clk_data = { + .clks = ap806_clks, + .clk_num = AP806_CLK_NUM, +}; + +static void __init ap806_syscon_clk_init(struct device_node *np) +{ + unsigned int freq_mode, cpuclk_freq; + const char *name, *fixedclk_name; + struct regmap *regmap; + u32 reg; + + regmap = syscon_node_to_regmap(np); + if (IS_ERR(regmap)) { + pr_err("cannot get regmap\n"); + return; + } + + if (regmap_read(regmap, AP806_SAR_REG, ®)) { + pr_err("cannot read from regmap\n"); + return; + } + + freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; + switch(freq_mode) { + case 0x0 ... 0x5: + cpuclk_freq = 2000; + break; + case 0x6 ... 0xB: + cpuclk_freq = 1800; + break; + case 0xC ... 0x11: + cpuclk_freq = 1600; + break; + case 0x12 ... 0x16: + cpuclk_freq = 1400; + break; + case 0x17 ... 0x19: + cpuclk_freq = 1300; + break; + default: + pr_err("invalid SAR value\n"); + return; + } + + /* Convert to hertz */ + cpuclk_freq *= 1000 * 1000; + + /* CPU clocks depend on the Sample At Reset configuration */ + of_property_read_string_index(np, "clock-output-names", + 0, &name); + ap806_clks[0] = clk_register_fixed_rate(NULL, name, NULL, + 0, cpuclk_freq); + + of_property_read_string_index(np, "clock-output-names", + 1, &name); + ap806_clks[1] = clk_register_fixed_rate(NULL, name, NULL, 0, + cpuclk_freq); + + /* Fixed clock is always 1200 Mhz */ + of_property_read_string_index(np, "clock-output-names", + 2, &fixedclk_name); + ap806_clks[2] = clk_register_fixed_rate(NULL, fixedclk_name, NULL, 0, + 1200 * 1000 * 1000); + + /* MSS Clock is fixed clock divided by 6 */ + of_property_read_string_index(np, "clock-output-names", + 3, &name); + ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name, + 0, 1, 6); + + of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); +} + +CLK_OF_DECLARE(ap806_syscon_clk, "marvell,ap806-system-controller", + ap806_syscon_clk_init);