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Mon, 7 Mar 2016 03:35:00 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.68]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u273Yr6f009628; Sun, 6 Mar 2016 20:34:54 -0700 From: Minghuan Lian To: , Subject: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Date: Mon, 7 Mar 2016 11:36:21 +0800 Message-ID: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131017953003862830; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11OLC004; 1:vl5RxAfcb1qBZacUVaZz9nIc3Q2fKjuCwDlWqxYyT8H7NQQF8dpfjgYLjr5ZITyBbGNfaztkQ8E/sR27fQnyEWCfTaLV/oerHtBd0sGR+9Xcsm2OwrBcWLCiJCRlA+fYsBp7UXMGP4znsHUkwD/luK41lqnW7U7+SC9gtJYFBFKkSAFg1oauKxff7jo1Ykt8r4KLs1znCWa4eoQUjV+f14R8Hfohdnkh72jPrNElpfhWY1DzegM1truRU7sNSDgh2fJqbwUDnLMGV81EDktRpkINYJNmVyaTv+XKjjjVqjTBhcv2FQfXFlzTGvQyoulzrF9sYddBMjKJ1iq30nVzQqMnD5EFbuThooENV/0ZemH7iqTCo1WjNm2rQjyKP+WqGBesWivcFu/rYNY7+iAOsJbnF1/z38Cz4P49fM26bpYY8q8vaGJjHO96iRryjhlG3wrwjBVcJmPdKg+kmEFSG8uoJ9R0FGGuSzbnrWVPepNhusEORQO/U1AxuUaGAdwnt/3QAisLSaYSsU1S1oAKFEAvtPjAq1+haiqKeMQyHZbPiCMoA1R46Q5JtdOVs9Cfn1J81/XdeLBs0j0OxvewuXncyiPngfYYQJMJu1pH808= X-Forefront-Antispam-Report: CIP:192.88.168.50; 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It contains only two SCFG register to trigger and describe a group 32 MSI interrupts. The patch adds bindings to describe the controller. Signed-off-by: Minghuan Lian --- change log: v4: add interrupt-parent description v3-v1: no change .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt new file mode 100644 index 0000000..9e38949 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt @@ -0,0 +1,30 @@ +* Freescale Layerscape SCFG PCIe MSI controller + +Required properties: + +- compatible: should be "fsl,-msi" to identify + Layerscape PCIe MSI controller block such as: + "fsl,1s1021a-msi" + "fsl,1s1043a-msi" +- msi-controller: indicates that this is a PCIe MSI controller node +- reg: physical base address of the controller and length of memory mapped. +- interrupts: an interrupt to the parent interrupt controller. + +Optional properties: +- interrupt-parent: the phandle to the parent interrupt controller. + +This interrupt controller hardware is a second level interrupt controller that +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based +platforms. If interrupt-parent is not provided, the default parent interrupt +controller will be used. +Each PCIe node needs to have property msi-parent that points to +MSI controller node + +Examples: + + msi1: msi-controller@1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x8>, + msi-controller; + interrupts = <0 116 0x4>; + };