From patchwork Mon Mar 7 20:39:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Franklin Cooper X-Patchwork-Id: 8523051 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DC8ABC0553 for ; Mon, 7 Mar 2016 20:43:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 052FC2012D for ; Mon, 7 Mar 2016 20:43:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05A6320254 for ; Mon, 7 Mar 2016 20:43:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ad1yE-0005h1-2d; Mon, 07 Mar 2016 20:41:38 +0000 Received: from mail-oi0-f50.google.com ([209.85.218.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ad1wu-0003jb-0d for linux-arm-kernel@lists.infradead.org; Mon, 07 Mar 2016 20:40:20 +0000 Received: by mail-oi0-f50.google.com with SMTP id r187so88088354oih.3 for ; Mon, 07 Mar 2016 12:39:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AuKsp4P7gCk00UCHGL0tPHbDgdndwkv/hxd43rINivA=; b=QGBa1k7AzhTcvlXnv3deyBLNCnbjrycZO3sihr6UsozwJxJtSBC3yLWfNV9hnvJcD5 hS3wf4GRP0ObpuPaq+B40ESSNhXzez25ralk7Cwt2ZcFULc6mzA+1Ey+RUfr8dDDmplC I4+83t0oOqh64lS1Q2PA1Two5F7YG8O4FFxhdxE309efc3xPyDxbNH/tKxxi/E29lOvb 2v2kLBQ4/KAcP0V20DvKct6FAUH/4RfIDjgF1uyUyb4CiArh/iCoE++dOMtDWVsLOMuB 9/MRyz2CyUokz7pBwDeFMkF3pW3xsr+hHCVPTap22AL728bKVm9P8IayuTcu1U111eA3 IPdA== X-Gm-Message-State: AD7BkJJ4pWjAM18wfA7NnQWhD6buO4AxiK0u+MCjL3JPRCLgiNJyKXNjkVi7ANzevTLmmg== X-Received: by 10.202.71.140 with SMTP id u134mr15046814oia.75.1457383194999; Mon, 07 Mar 2016 12:39:54 -0800 (PST) Received: from beast-server.fios-router.home (pool-173-57-21-86.dllstx.fios.verizon.net. [173.57.21.86]) by smtp.gmail.com with ESMTPSA id s3sm10657547obf.29.2016.03.07.12.39.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Mar 2016 12:39:54 -0800 (PST) From: Franklin S Cooper Jr To: vigneshr@ti.com, thierry.reding@gmail.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, bcousson@baylibre.com, tony@atomide.com, paul@pwsan.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [Patch v4 6/6] ARM: dts: DRA7: Add dt nodes for PWMSS Date: Mon, 7 Mar 2016 14:39:47 -0600 Message-Id: <1457383187-17166-7-git-send-email-fcooper@ti.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1457383187-17166-1-git-send-email-fcooper@ti.com> References: <1457383187-17166-1-git-send-email-fcooper@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160307_124016_353973_9038FD21 X-CRM114-Status: GOOD ( 12.35 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Franklin S Cooper Jr MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vignesh R Add PWMSS device tree nodes for DRA7 SoC family and add documentation for dt bindings. Signed-off-by: Vignesh R [fcooper@ti.com: Use updated bindings for PWMSS and ePWM] Signed-off-by: Franklin S Cooper Jr --- Version 4 changes: Remove hwmod entries. Add clocks/clock-names to pwm nodes. .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 ++++ .../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++++- arch/arm/boot/dts/dra7.dtsi | 60 ++++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 345d3f6..5965b9d 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must be "ti,-ehrpwm". for am33xx - compatible = "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -28,3 +29,11 @@ ehrpwm0: pwm@01f00000 { /* EHRPWM on da850 */ #pwm-cells = <3>; reg = <0x300000 0x2000>; }; + +ehrpwm0: pwm@4843e200 { /* EHRPWM on dra7xx */ + compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index 672fa71..f137d0b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -1,7 +1,9 @@ TI SOC based PWM Subsystem Required properties: -- compatible: Must be "ti,am33xx-pwmss"; +- compatible: Must be "ti,-pwmss". + for am33xx - compatible = "ti,am33xx-pwmss" + for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss" - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. @@ -25,3 +27,14 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; + +epwmss0: epwmss@4843e000 { /* On DRA7xx */ + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* child nodes go here */ +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c4d9175..cc161b3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1597,6 +1597,66 @@ clock-names = "fck", "sys_clk"; }; }; + + epwmss0: epwmss@4843e000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm0: pwm@4843e200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48440000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x48440000 0x30>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm1: pwm@48440200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm1_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48442000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x48442000 0x30>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm2: pwm@48442200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48442200 0x80>; + clocks = <&ehrpwm2_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + }; }; thermal_zones: thermal-zones {