@@ -215,6 +215,24 @@ static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80);
}
+static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
+{
+ int hwirq, start_hwirq;
+ struct irq_desc *desc;
+
+ if (pdata->rm == RM0)
+ start_hwirq = XGENE1_RM0_START_IRQ;
+ else if (pdata->rm == RM1)
+ start_hwirq = XGENE1_RM1_START_IRQ;
+ else
+ start_hwirq = XGENE1_RM3_START_IRQ;
+
+ desc = irq_to_desc(pdata->irqs[0]);
+ hwirq = desc->irq_data.hwirq;
+
+ return hwirq - start_hwirq;
+}
+
void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
struct xgene_enet_pdata *pdata,
enum xgene_enet_err_code status)
@@ -904,4 +922,5 @@ struct xgene_ring_ops xgene_ring1_ops = {
.wr_cmd = xgene_enet_wr_cmd,
.len = xgene_enet_ring_len,
.coalesce = xgene_enet_setup_coalescing,
+ .start_cpu_bufnum = xgene_start_cpu_bufnum,
};
@@ -300,6 +300,12 @@ enum xgene_enet_cmd {
XGENE_ENET_RD_CMD = BIT(30)
};
+enum xgene_enet1_rm_start_irq {
+ XGENE1_RM0_START_IRQ = 128,
+ XGENE1_RM1_START_IRQ = 192,
+ XGENE1_RM3_START_IRQ = 92,
+};
+
enum xgene_enet_err_code {
HBF_READ_DATA = 3,
HBF_LL_READ = 4,
@@ -981,13 +981,15 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
struct xgene_enet_desc_ring *buf_pool = NULL;
enum xgene_ring_owner owner;
dma_addr_t dma_exp_bufs;
- u8 cpu_bufnum = pdata->cpu_bufnum;
+ u8 cpu_bufnum;
u8 eth_bufnum = pdata->eth_bufnum;
u8 bp_bufnum = pdata->bp_bufnum;
u16 ring_num = pdata->ring_num;
u16 ring_id;
int i, ret, size;
+ cpu_bufnum = pdata->ring_ops->start_cpu_bufnum(pdata);
+
for (i = 0; i < pdata->rxq_cnt; i++) {
/* allocate rx descriptor ring */
owner = xgene_derive_ring_owner(pdata);
@@ -1446,19 +1448,16 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
if (pdata->enet_id == XGENE_ENET1) {
switch (pdata->port_id) {
case 0:
- pdata->cpu_bufnum = START_CPU_BUFNUM_0;
pdata->eth_bufnum = START_ETH_BUFNUM_0;
pdata->bp_bufnum = START_BP_BUFNUM_0;
pdata->ring_num = START_RING_NUM_0;
break;
case 1:
if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
- pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
pdata->ring_num = XG_START_RING_NUM_1;
} else {
- pdata->cpu_bufnum = START_CPU_BUFNUM_1;
pdata->eth_bufnum = START_ETH_BUFNUM_1;
pdata->bp_bufnum = START_BP_BUFNUM_1;
pdata->ring_num = START_RING_NUM_1;
@@ -1471,13 +1470,11 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
} else {
switch (pdata->port_id) {
case 0:
- pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
pdata->ring_num = X2_START_RING_NUM_0;
break;
case 1:
- pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
pdata->ring_num = X2_START_RING_NUM_1;
@@ -54,25 +54,20 @@
#define XGENE_NUM_TX_RING 4
#define XGENE_NUM_TXC_RING 4
-#define START_CPU_BUFNUM_0 0
#define START_ETH_BUFNUM_0 2
#define START_BP_BUFNUM_0 0x22
#define START_RING_NUM_0 8
-#define START_CPU_BUFNUM_1 12
#define START_ETH_BUFNUM_1 10
#define START_BP_BUFNUM_1 0x2A
#define START_RING_NUM_1 264
-#define XG_START_CPU_BUFNUM_1 12
#define XG_START_ETH_BUFNUM_1 2
#define XG_START_BP_BUFNUM_1 0x22
#define XG_START_RING_NUM_1 264
-#define X2_START_CPU_BUFNUM_0 0
#define X2_START_ETH_BUFNUM_0 0
#define X2_START_BP_BUFNUM_0 0x20
#define X2_START_RING_NUM_0 0
-#define X2_START_CPU_BUFNUM_1 0xc
#define X2_START_ETH_BUFNUM_1 0
#define X2_START_BP_BUFNUM_1 0x20
#define X2_START_RING_NUM_1 256
@@ -150,6 +145,7 @@ struct xgene_ring_ops {
void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
u32 (*len)(struct xgene_enet_desc_ring *);
void (*coalesce)(struct xgene_enet_desc_ring *);
+ u8 (*start_cpu_bufnum)(struct xgene_enet_pdata *);
};
struct xgene_cle_ops {
@@ -194,7 +190,6 @@ struct xgene_enet_pdata {
struct xgene_cle_ops *cle_ops;
struct delayed_work link_work;
u32 port_id;
- u8 cpu_bufnum;
u8 eth_bufnum;
u8 bp_bufnum;
u16 ring_num;
@@ -201,6 +201,17 @@ static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80);
}
+static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
+{
+ struct irq_desc *desc;
+ int hwirq;
+
+ desc = irq_to_desc(pdata->irqs[0]);
+ hwirq = desc->irq_data.hwirq;
+
+ return hwirq - XGENE2_RM0_START_IRQ;
+}
+
struct xgene_ring_ops xgene_ring2_ops = {
.num_ring_config = X2_NUM_RING_CONFIG,
.num_ring_id_shift = 13,
@@ -209,4 +220,5 @@ struct xgene_ring_ops xgene_ring2_ops = {
.wr_cmd = xgene_enet_wr_cmd,
.len = xgene_enet_ring_len,
.coalesce = xgene_enet_setup_coalescing,
+ .start_cpu_bufnum = xgene_start_cpu_bufnum,
};
@@ -44,6 +44,10 @@
#define X2_NUMMSGSINQ_POS 0
#define X2_NUMMSGSINQ_LEN 17
+enum xgene_enet2_rm_start_irq {
+ XGENE2_RM0_START_IRQ = 128,
+};
+
extern struct xgene_ring_ops xgene_ring2_ops;
#endif /* __XGENE_ENET_RING2_H__ */