From patchwork Wed Mar 9 10:24:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8544701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2FD729F2B4 for ; Wed, 9 Mar 2016 10:27:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 292B1200FF for ; Wed, 9 Mar 2016 10:27:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2858420121 for ; Wed, 9 Mar 2016 10:27:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1adbJg-0003ic-LG; Wed, 09 Mar 2016 10:26:08 +0000 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1adbIn-00027k-GU for linux-arm-kernel@lists.infradead.org; Wed, 09 Mar 2016 10:25:16 +0000 Received: by mail-wm0-x234.google.com with SMTP id l68so170973357wml.0 for ; Wed, 09 Mar 2016 02:24:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ftB4GD83m5M0UA4yUJKcUhhkdy4qMU5GS+t3f7xQgcc=; b=2Gtlo8Lg2IuFyH1Kv6VX4sdgswPKNcbhn2w3TZewZiH9ue2h7ClcdtznXiNEle4LeT ZlsCiPjj7R6GNHgQFUZO6w4uMxlVBbWU8PwTZD49fJ8KklxxWHGla8x/Y0ckg9NlE+bL bOoM8uwovoogJG7uHkKGKA3E7I4lVfJCtTzOYzMGYSkrtT2JTeGMksDfw60aqi9eFsjX EAAt7GtnNwI9iLG9/oHpEMncmnHooNP19hgQCDMSJxuti+xHNmzsZAvnQs9Vf0aHbT46 Clalbxz1SjZQvdv5ZJOwPEVjsuBauVSUBpMqaTM4M1N5hUXewAzNyJvX1mepw8vPqfxb XonQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ftB4GD83m5M0UA4yUJKcUhhkdy4qMU5GS+t3f7xQgcc=; b=Pg1D1AIyN2kvWm5OEBhXNtj7hUJ5qxEhJaNXZC4e/OViJvwx18Obkl+UpF5f905X+M FZ86x9hkLjOcU7Y9vWw1k8eERlePfzSHv1zxRFGuX+xmPjVhsWUd3nnTBkMPV3GNybbg pNnquQ8fL1iTS/8R2+WFAsmjF/9mTrmiAkN57P5F9rNEP/sX0Csjt97ZrvYXK+20pQ5X yRohfxMVK2gtY60OcWgzsQYTurrMpv3bvDZsT1K1Ot+TKLiZw3V/UZiQiwVVnscbohaN lvw+VAUPE6aJ5DxRRD7An2IsHyAWEoneJAbL9vg1K06sxpIIbMtEXXjztMHNY09Sf1cM LCBg== X-Gm-Message-State: AD7BkJIDdGr5mXP8kqMNA3plo1WWajYUqP+dz7MS6EYXxITcsu4QbYP/kkFxpbbLetiflUuF X-Received: by 10.28.0.148 with SMTP id 142mr14492983wma.72.1457519090885; Wed, 09 Mar 2016 02:24:50 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id n66sm7648305wmg.20.2016.03.09.02.24.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Mar 2016 02:24:50 -0800 (PST) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, daniel.lezcano@linaro.org, tglx@linutronix.de, rmk+kernel@arm.linux.org.uk, sudeep.holla@arm.com Subject: [PATCH v2 01/18] clocksource: sp804: Add support for non-32bit width counter Date: Wed, 9 Mar 2016 11:24:03 +0100 Message-Id: <1457519060-6038-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160309_022513_780661_646F918E X-CRM114-Status: GOOD ( 14.83 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some vendor variants can implement norrower counter width, add an optional DT property changing the clocksource width and the clockevent mask, but keeping 32bit as default for legacy interface. Signed-off-by: Neil Armstrong --- drivers/clocksource/timer-sp804.c | 38 +++++++++++++++++++++++++++----------- include/clocksource/timer-sp804.h | 11 ++++++----- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 5f45b9a..8acf524 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -80,7 +80,8 @@ void __init sp804_timer_disable(void __iomem *base) void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name, struct clk *clk, - int use_sched_clock) + int use_sched_clock, + unsigned width) { long rate; @@ -93,6 +94,9 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, } } + if (!width || width > 32) + width = 32; + rate = sp804_get_clock_rate(clk); if (rate < 0) @@ -106,11 +110,11 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, base + TIMER_CTRL); clocksource_mmio_init(base + TIMER_VALUE, name, - rate, 200, 32, clocksource_mmio_readl_down); + rate, 200, width, clocksource_mmio_readl_down); if (use_sched_clock) { sched_clock_base = base; - sched_clock_register(sp804_read, 32, rate); + sched_clock_register(sp804_read, width, rate); } } @@ -186,7 +190,9 @@ static struct irqaction sp804_timer_irq = { .dev_id = &sp804_clockevent, }; -void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) +void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, + struct clk *clk, const char *name, + unsigned width) { struct clock_event_device *evt = &sp804_clockevent; long rate; @@ -199,6 +205,9 @@ void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struc return; } + if (!width || width > 32) + width = 32; + rate = sp804_get_clock_rate(clk); if (rate < 0) return; @@ -212,7 +221,7 @@ void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struc writel(0, base + TIMER_CTRL); setup_irq(irq, &sp804_timer_irq); - clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); + clockevents_config_and_register(evt, rate, 0xf, GENMASK(width-1, 0)); } static void __init sp804_of_init(struct device_node *np) @@ -223,6 +232,7 @@ static void __init sp804_of_init(struct device_node *np) u32 irq_num = 0; struct clk *clk1, *clk2; const char *name = of_get_property(np, "compatible", NULL); + u32 width = 32; base = of_iomap(np, 0); if (WARN_ON(!base)) @@ -254,14 +264,19 @@ static void __init sp804_of_init(struct device_node *np) if (irq <= 0) goto err; + /* Some vendor variants can have a different counter width */ + of_property_read_u32(np, "arm,timer-width", &width); + of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { - __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); - __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); + __sp804_clockevents_init(base + TIMER_2_BASE, irq, + clk2, name, width); + __sp804_clocksource_and_sched_clock_init(base, name, + clk1, 1, width); } else { - __sp804_clockevents_init(base, irq, clk1 , name); + __sp804_clockevents_init(base, irq, clk1, name, width); __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, - name, clk2, 1); + name, clk2, 1, width); } initialized = true; @@ -293,13 +308,14 @@ static void __init integrator_cp_of_init(struct device_node *np) goto err; if (!init_count) - __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); + __sp804_clocksource_and_sched_clock_init(base, name, + clk, 0, 32); else { irq = irq_of_parse_and_map(np, 0); if (irq <= 0) goto err; - __sp804_clockevents_init(base, irq, clk, name); + __sp804_clockevents_init(base, irq, clk, name, 32); } init_count++; diff --git a/include/clocksource/timer-sp804.h b/include/clocksource/timer-sp804.h index 1f8a1ca..ad71fcb 100644 --- a/include/clocksource/timer-sp804.h +++ b/include/clocksource/timer-sp804.h @@ -4,25 +4,26 @@ struct clk; void __sp804_clocksource_and_sched_clock_init(void __iomem *, - const char *, struct clk *, int); + const char *, struct clk *, + int, unsigned); void __sp804_clockevents_init(void __iomem *, unsigned int, - struct clk *, const char *); + struct clk *, const char *, unsigned); void sp804_timer_disable(void __iomem *); static inline void sp804_clocksource_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); + __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0, 32); } static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); + __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1, 32); } static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) { - __sp804_clockevents_init(base, irq, NULL, name); + __sp804_clockevents_init(base, irq, NULL, name, 32); } #endif