From patchwork Wed Mar 9 18:44:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 8548451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1132BC0553 for ; Wed, 9 Mar 2016 18:47:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E37122021A for ; Wed, 9 Mar 2016 18:47:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C8657200EC for ; Wed, 9 Mar 2016 18:47:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1adj6w-0008MY-Gy; Wed, 09 Mar 2016 18:45:30 +0000 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1adj6Z-000761-5Q for linux-arm-kernel@lists.infradead.org; Wed, 09 Mar 2016 18:45:09 +0000 Received: by mail-pf0-x22d.google.com with SMTP id 124so47743621pfg.0 for ; Wed, 09 Mar 2016 10:44:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=Q/iqs4fB2S/svkJBitsR2twZe2ZyUNYUREB7y902fUo=; b=h1qf0chI/yVWjaW/rLaCOAoFX87ymVTi02F+4OZAQjohzNGofYf6qc26pO+rpGYCCV 95k9f7RDUVDoGg5xCBe2GY9FTRdZNAGfpH+qXd+PgZHb2JgMvJ65HabdDgOKGqBwyyQM aBjsDNv/KcK2igO+KLdn3sIz/tWuacwBArzJE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Q/iqs4fB2S/svkJBitsR2twZe2ZyUNYUREB7y902fUo=; b=ehupbVwY5vCgCqKPe+ZXBbUXBisYlcttvrmf9Frg3oRCSf469w8BNEqkZf21dxqsE/ qCyc/yGoQZ6XglNf/rQclstgjcRVRNqdxwwhga68JNo2Ayso98Xr5OTkV6vuW82MInay 56Gd+AkFLty9ZaU9pBgEuugpXJ4Z+gOivOcs4bUntP1OM8MDOwJoMmQ7N1NS7gAQMUwV Uxl6eiLMhd+CNr15RKTkxElp3P6SnURAXhl5vpLgrs6pj4AgmY4r7L78ALJg03om0mSl f+3t3mN/3EIfLOfS5L/MlmWqDOicuyy5V1DfhMUMVPxSBFRAnIhptCamq4tgl9TM+lUv cXCA== X-Gm-Message-State: AD7BkJLIpn7fIU8mTUBYGXoBumcdatru/vLy75GiecRnysRI96K3r2jY2uJSdL3jY/ocgg== X-Received: by 10.98.14.149 with SMTP id 21mr52137914pfo.79.1457549084858; Wed, 09 Mar 2016 10:44:44 -0800 (PST) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id x18sm14025451pfi.42.2016.03.09.10.44.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Mar 2016 10:44:43 -0800 (PST) From: Douglas Anderson To: Russell King , Will Deacon , Heiko Stuebner , Matthias Brugger Subject: [PATCH v2 1/3] ARM: errata: Workaround errata A12 818325/852422 A17 852423 Date: Wed, 9 Mar 2016 10:44:14 -0800 Message-Id: <1457549056-22359-1-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160309_104507_331187_E1BE1F69 X-CRM114-Status: GOOD ( 16.54 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huang Tao , nicolas.pitre@linaro.org, shawn.guo@linaro.org, ard.biesheuvel@linaro.org, linux-kernel@vger.kernel.org, Anson.Huang@freescale.com, Douglas Anderson , Kever Yang , linux-rockchip@lists.infradead.org, olof@lixom.net, treding@nvidia.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are several similar errata on Cortex A12 and A17 that all have the same workaround: setting bit[12] of the Feature Register. Technically the list of errata are: - A12 818325: Execution of an UNPREDICTABLE STR or STM instruction might deadlock. Fixed in r0p1. - A12 852422: Execution of a sequence of instructions might lead to either a data corruption or a CPU deadlock. Not fixed in any A12s yet. - A17 852423: Execution of a sequence of instructions might lead to either a data corruption or a CPU deadlock. Not fixed in any A17s yet. Since A12 got renamed to A17 it seems likely that there won't be any future Cortex-A12 cores, so we'll enable for all Cortex-A12. For Cortex-A17 I believe that all known revisions are affected and that all knows revisions means <= r1p2. Presumably if a new A17 was released it would have this problem fixed. Note that in folks previously expressed opposition to this change because: A) It was thought to only apply to r0p0 and there were no known r0p0 boards supported in mainline. B) It was argued that such a workaround beloned in firmware. Now that this same fix solves other errata on real boards (like rk3288) point A) is addressed. Point B) is impossible to address on boards like rk3288. On rk3288 the firmware doesn't stay resident in RAM and isn't involved at all in the suspend/resume process nor in the SMP bringup process. That means that the most the firmware could do would be to set the bit on "core 0" and this bit would be lost at suspend/resume time. It is true that we could write a "generic" solution that saved the boot-time "core 0" value of this register and applied it at SMP bringup / resume time. However, since this register (described as the "Feature Register" in errata) appears to be undocumented (as far as I can tell) and is only modified for these errata, that "generic" solution seems questionably cleaner. The generic solution also won't fix existing users that haven't happened to do a FW update. Note that in ARM64 presumably PSCI will be universal and fixes like this will end up in ATF. Hopefully we are nearing the end of this style of errata workaround. Signed-off-by: Douglas Anderson Signed-off-by: Huang Tao Signed-off-by: Kever Yang --- Changes in v2: None arch/arm/Kconfig | 26 ++++++++++++++++++++++++++ arch/arm/mm/proc-v7.S | 27 +++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4f799e567fc8..a5e16e4e796b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1157,6 +1157,32 @@ config ARM_ERRATA_773022 loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum. +config ARM_ERRATA_818325_852422 + bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" + depends on CPU_V7 + help + This option enables the workaround for: + - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM + instruction might deadlock. Fixed in r0p1. + - Cortex-A12 852422: Execution of a sequence of instructions might + lead to either a data corruption or a CPU deadlock. Not fixed in + any Cortex-A12 cores yet. + This workaround for all both errata involves setting bit[12] of the + Feature Register. This bit disables an optimisation applied to a + sequence of 2 instructions that use opposing condition codes. + +config ARM_ERRATA_852423 + bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" + depends on CPU_V7 + help + This option enables the workaround for: + - Cortex-A17 852423: Execution of a sequence of instructions might + lead to either a data corruption or a CPU deadlock. Not fixed in + any Cortex-A17 cores yet. + This is identical to Cortex-A12 erratum 852422. It is a separate + config option from the A12 erratum due to the way errata are checked + for and handled. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 0f92d575a304..6cea0435f3f2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -362,6 +362,23 @@ __ca15_errata: #endif b __errata_finish +__ca12_errata: +#ifdef CONFIG_ARM_ERRATA_818325_852422 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 12 @ set bit #12 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif + b __errata_finish + +__ca17_errata: +#ifdef CONFIG_ARM_ERRATA_852423 + cmp r6, #0x12 @ only present up to r1p2 + mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrle r10, r10, #1 << 12 @ set bit #12 + mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif + b __errata_finish + __v7_pj4b_setup: #ifdef CONFIG_CPU_PJ4B @@ -443,6 +460,16 @@ __v7_setup_cont: teq r0, r10 beq __ca9_errata + /* Cortex-A12 Errata */ + ldr r10, =0x00000c0d @ Cortex-A12 primary part number + teq r0, r10 + beq __ca12_errata + + /* Cortex-A17 Errata */ + ldr r10, =0x00000c0e @ Cortex-A17 primary part number + teq r0, r10 + beq __ca17_errata + /* Cortex-A15 Errata */ ldr r10, =0x00000c0f @ Cortex-A15 primary part number teq r0, r10