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Mon, 14 Mar 2016 11:04:23 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Subject: [PATCH 02/10] clk: samsung: exynos3250: Add MMC2 clock Date: Mon, 14 Mar 2016 11:04:07 +0900 Message-id: <1457921056-21257-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1457921056-21257-1-git-send-email-cw00.choi@samsung.com> References: <1457921056-21257-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsWyRsSkUFdd5lmYweR9Ghbbjzxjtbj+5Tmr xfwj51gtJt2fwGJx41cbq8XrF4YW/Y9fM1tsenyN1eLyrjlsFjPO72OyWLT1C7vF4TftrBYz Jr9ks1i16w+jA5/Hzll32T02repk89i8pN6jb8sqRo/Pm+QCWKO4bFJSczLLUov07RK4Mn4f mcVYsEO2YsLOHawNjMcluhg5OSQETCR+Nlxmg7DFJC7cWw9kc3EICaxglNg96RgjTNH+ycvZ QWwhgVmMEieasyGKvjBKbG+cwAySYBPQktj/4gbYJBGBOImJFyFsZoFZTBLz5heC2MIC9hJb Xu1h6WLk4GARUJW4uM0AxOQVcJX4vCcdYpWcxIc9j8BWcQq4Sew68ooVYq2rxL7bJxhB1koI nGOXeHB3L9haFgEBiW+TD4GNlBCQldh0gBlijqTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKxX nJhbXJqXrpecn7uJERglp/8969/BePeA9SFGAQ5GJR7eH2uehgmxJpYVV+YeYjQF2jCRWUo0 OR8Yi3kl8YbGZkYWpiamxkbmlmZK4rwLpX4GCwmkJ5akZqemFqQWxReV5qQWH2Jk4uCUamCs dBbZckEiYf3+zKeLveutlu6M1xPdXb1Y+Rj35F9Jfi7HdR7Pq9D9ptSncnuKqWns5z5Js6Mr Ls4MlviV7bupqUX0Z5sUR+p7hyv3pX4f8NfZ67eRz1TuU37tVCnZM3FdrFuPXPCVXN3c8UP9 QgHHMnYZOR1+a/lbqUf4il9uNtBw0H+x/7QSS3FGoqEWc1FxIgBXi0bkjQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQV11mWdhBjuuKFlsP/KM1eL6l+es FvOPnGO1mHR/AovFjV9trBavXxha9D9+zWyx6fE1VovLu+awWcw4v4/JYtHWL+wWh9+0s1rM mPySzWLVrj+MDnweO2fdZffYtKqTzWPzknqPvi2rGD0+b5ILYI1qYLTJSE1MSS1SSM1Lzk/J zEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQdcvMATpUSaEsMacUKBSQWFyspG+HaUJo iJuuBUxjhK5vSBBcj5EBGkhYw5jx+8gsxoIdshUTdu5gbWA8LtHFyMkhIWAisX/ycnYIW0zi wr31bCC2kMAsRokTzdldjFxA9hdGie2NE5hBEmwCWhL7X9wAKxIRiJOYeBHCZhaYxSQxb34h iC0sYC+x5dUeli5GDg4WAVWJi9sMQExeAVeJz3vSIVbJSXzY8whsLaeAm8SuI69YIda6Suy7 fYJxAiPvAkaGVYwSqQXJBcVJ6blGeanlesWJucWleel6yfm5mxjBkfhMegfj4V3uhxgFOBiV eHh/rHkaJsSaWFZcmXuIUYKDWUmE11vyWZgQb0piZVVqUX58UWlOavEhRlOgsyYyS4km5wOT RF5JvKGxiZmRpZG5oYWRsbmSOO/j/+vChATSE0tSs1NTC1KLYPqYODilGhiTo3/PKTLbmljw L8lY5eCHkwW6t+bM/LHouUHTxMzpOVOrX/5Ou3I2KI9H692TKeF3Iu4dmZq6Vz3RfEWTgONs p/6ldaJVl6MWeL9y0e8+cedazdTnnV83v/flcWj6q1b9ct/HRzeyTY57b3v+fqfZ7hVKRZf0 lBQObdCU0oiZd8HzdGr+v0WdSizFGYmGWsxFxYkA+qjFj9oCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160313_190446_217675_3685C063 X-CRM114-Status: GOOD ( 11.71 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, pankaj.dubey@samsung.com, sw0312.kim@samsung.com, linux-kernel@vger.kernel.org, andi.shyti@samsung.com, jh80.chung@samsung.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++ include/dt-bindings/clock/exynos3250.h | 7 ++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index bc60e399d1bc..16575ee874cb 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { /* SRC_FSYS */ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), @@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + /* DIV_FSYS2 */ + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, + CLK_SET_RATE_PARENT, 0), + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + /* DIV_PERIL0 */ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), @@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", @@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index ddb874130d86..c796ff02ceeb 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -80,6 +80,7 @@ #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -129,6 +130,8 @@ #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 #define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -226,6 +229,7 @@ #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 #define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -253,12 +257,13 @@ #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 #define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 249 +#define CLK_NR_CLKS 250 /* * CMU DMC