| Message ID | 1458285444-31129-2-git-send-email-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Elaine Zhang <zhangqing@rock-chips.com> writes: > Add qos example for power domain which found on Rockchip SoCs. > These qos register description in TRMs > (rk3036, rk3228, rk3288, rk3366, rk3368, rk3399) looks the same. This should describe in more detail what "qos" is in this context. At first glance, it's just a range of registers that lose context that need to be saved/restored. Kevin
Am Freitag, 18. März 2016, 09:18:51 schrieb Kevin Hilman: > Elaine Zhang <zhangqing@rock-chips.com> writes: > > Add qos example for power domain which found on Rockchip SoCs. > > These qos register description in TRMs > > (rk3036, rk3228, rk3288, rk3366, rk3368, rk3399) looks the same. > > This should describe in more detail what "qos" is in this context. At > first glance, it's just a range of registers that lose context that need > to be saved/restored. I guess that should be something like ---- 8< ---- Rockchip SoCs contain quality of service (qos) blocks managing priority, bandwidth, etc of the connection of each domain to the interconnect. These blocks loose state when their domain gets disabled and therefore need to be saved when disabling and restored when enabling a power-domain. These qos blocks also are similar over all currently available Rockchip SoCs. ---- 8< ----
Hi Kevin, Am Freitag, 18. März 2016, 23:16:55 schrieb Heiko Stuebner: > Am Freitag, 18. März 2016, 09:18:51 schrieb Kevin Hilman: > > Elaine Zhang <zhangqing@rock-chips.com> writes: > > > Add qos example for power domain which found on Rockchip SoCs. > > > These qos register description in TRMs > > > (rk3036, rk3228, rk3288, rk3366, rk3368, rk3399) looks the same. > > > > This should describe in more detail what "qos" is in this context. At > > first glance, it's just a range of registers that lose context that need > > to be saved/restored. > > I guess that should be something like > > ---- 8< ---- > Rockchip SoCs contain quality of service (qos) blocks managing priority, > bandwidth, etc of the connection of each domain to the interconnect. > These blocks loose state when their domain gets disabled and therefore > need to be saved when disabling and restored when enabling a power-domain. > > These qos blocks also are similar over all currently available Rockchip > SoCs. > ---- 8< ---- does this look sane to you in terms of description, or do we need something more? Heiko
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt index 13dc6a3..5a61d36 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt @@ -19,6 +19,13 @@ Required properties for power domain sub nodes: - clocks (optional): phandles to clocks which need to be enabled while power domain switches state. +Qos Example: + + qos_gpu: qos_gpu@ffaf0000 { + compatible ="syscon"; + reg = <0x0 0xffaf0000 0x0 0x20>; + }; + Example: power: power-controller { @@ -30,6 +37,7 @@ Example: pd_gpu { reg = <RK3288_PD_GPU>; clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; }; };
Add qos example for power domain which found on Rockchip SoCs. These qos register description in TRMs (rk3036, rk3228, rk3288, rk3366, rk3368, rk3399) looks the same. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- Documentation/devicetree/bindings/soc/rockchip/power_domain.txt | 8 ++++++++ 1 file changed, 8 insertions(+)