| Message ID | 1458576106-24505-10-git-send-email-tthayer@opensource.altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Mar 21, 2016 at 11:01:46AM -0500, tthayer@opensource.altera.com wrote: > From: Thor Thayer <tthayer@opensource.altera.com> > > Add the device tree entries needed to support the Altera L2 > cache EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> > --- > v2 Match register value (l2-ecc@ffd06010) > v3 Set ecc_manager to beginning of system_manager. Add sysman > phandle. Move IRQs into ecc_manager from children. > --- > arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi > index cce9e50..345ea97 100644 > --- a/arch/arm/boot/dts/socfpga_arria10.dtsi > +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi > @@ -599,6 +599,21 @@ > reg = <0xffe00000 0x40000>; > }; > > + eccmgr: eccmgr@ffd06000 { > + compatible = "altr,socfpga-a10-ecc-manager"; > + altr,sysmgr-syscon = <&sysmgr>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 IRQ_TYPE_LEVEL_HIGH>; > + ranges; > + > + l2-ecc@ffd06010 { > + compatible = "altr,socfpga-a10-l2-ecc"; > + reg = <0xffd06010 0x4>; > + }; > + }; > + > rst: rstmgr@ffd05000 { > #reset-cells = <1>; > compatible = "altr,rst-mgr"; > -- I've picked up all except this one: need an ACK for it too. Dinh, DT-people?
Hi Boris, On Tue, Mar 29, 2016 at 3:45 AM, Borislav Petkov <bp@alien8.de> wrote: > On Mon, Mar 21, 2016 at 11:01:46AM -0500, tthayer@opensource.altera.com wrote: >> From: Thor Thayer <tthayer@opensource.altera.com> >> >> Add the device tree entries needed to support the Altera L2 >> cache EDAC on the Arria10 chip. >> >> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> >> --- >> v2 Match register value (l2-ecc@ffd06010) >> v3 Set ecc_manager to beginning of system_manager. Add sysman >> phandle. Move IRQs into ecc_manager from children. >> --- >> arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi >> index cce9e50..345ea97 100644 >> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi >> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi >> @@ -599,6 +599,21 @@ >> reg = <0xffe00000 0x40000>; >> }; >> >> + eccmgr: eccmgr@ffd06000 { >> + compatible = "altr,socfpga-a10-ecc-manager"; >> + altr,sysmgr-syscon = <&sysmgr>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 IRQ_TYPE_LEVEL_HIGH>; >> + ranges; >> + >> + l2-ecc@ffd06010 { >> + compatible = "altr,socfpga-a10-l2-ecc"; >> + reg = <0xffd06010 0x4>; >> + }; >> + }; >> + >> rst: rstmgr@ffd05000 { >> #reset-cells = <1>; >> compatible = "altr,rst-mgr"; >> -- > > I've picked up all except this one: need an ACK for it too. Dinh, DT-people? > If you don't mind, I can take this patch. This will prevent merge conflicts in the DTS board files. Thanks, Dinh
On Tue, Mar 29, 2016 at 07:15:38AM -0500, Dinh Nguyen wrote: > If you don't mind, I can take this patch. This will prevent merge > conflicts in the > DTS board files. Fine with me as long as people don't start complaining if they start testing my for-next branch and realize that the Arria10 support is not complete. Unless they test linux-next where your tree is too, I assume.
On Tue, Mar 29, 2016 at 9:00 AM, Borislav Petkov <bp@alien8.de> wrote: > Fine with me as long as people don't start complaining if they start > testing my for-next branch and realize that the Arria10 support is not > complete. > > Unless they test linux-next where your tree is too, I assume. > Yes, I take the patch through arm-soc and will ultimately land in linux-next. Dinh
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index cce9e50..345ea97 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -599,6 +599,21 @@ reg = <0xffe00000 0x40000>; }; + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + ranges; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + }; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr";