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Wed, 23 Mar 2016 11:06:55 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.68]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u2NB6lEE014059; Wed, 23 Mar 2016 04:06:48 -0700 From: Minghuan Lian To: , , Subject: [PATCH 1/2 v6] dt/bindings: Add bindings for Layerscape SCFG MSI Date: Wed, 23 Mar 2016 19:08:19 +0800 Message-ID: <1458731300-13648-1-git-send-email-Minghuan.Lian@nxp.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131032048199820279; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(189998001)(5001770100001)(50226001)(229853001)(586003)(5003940100001)(4326007)(1220700001)(5008740100001)(2201001)(1096002)(105606002)(2906002)(87936001)(92566002)(47776003)(106466001)(36756003)(11100500001)(86362001)(19580405001)(85426001)(19580395003)(77096005)(104016004)(48376002)(6806005)(50986999)(50466002)(81166005)(7059030)(2101003); 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It contains only two SCFG register to trigger and describe a group 32 MSI interrupts. The patch adds bindings to describe the controller. Signed-off-by: Minghuan Lian Acked-by: Rob Herring --- change log: v6-v4: no change v4: add interrupt-parent description v3-v1: no change .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt new file mode 100644 index 0000000..9e38949 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt @@ -0,0 +1,30 @@ +* Freescale Layerscape SCFG PCIe MSI controller + +Required properties: + +- compatible: should be "fsl,-msi" to identify + Layerscape PCIe MSI controller block such as: + "fsl,1s1021a-msi" + "fsl,1s1043a-msi" +- msi-controller: indicates that this is a PCIe MSI controller node +- reg: physical base address of the controller and length of memory mapped. +- interrupts: an interrupt to the parent interrupt controller. + +Optional properties: +- interrupt-parent: the phandle to the parent interrupt controller. + +This interrupt controller hardware is a second level interrupt controller that +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based +platforms. If interrupt-parent is not provided, the default parent interrupt +controller will be used. +Each PCIe node needs to have property msi-parent that points to +MSI controller node + +Examples: + + msi1: msi-controller@1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x8>, + msi-controller; + interrupts = <0 116 0x4>; + };