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Thu, 24 Mar 2016 13:25:34 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Subject: [PATCH v5 16/21] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 Date: Thu, 24 Mar 2016 13:25:25 +0900 Message-id: <1458793530-31897-17-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1458793530-31897-1-git-send-email-cw00.choi@samsung.com> References: <1458793530-31897-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsWyRsSkWNcu53OYwcIuG4vrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BabHl9jtbi8aw6bxefeI4wWM87vY7JYt/EWu8Xt y7wWS69fZLK43biCzWLC9LUsFmdOX2K1aN17hN2ibfUHVgdhjzXz1jB6tDT3sHlc7utl8tg5 6y67x8rlX9g8Nq3qZPPYvKTe498xdo8tV9tZPPq2rGL0+LxJLoA7issmJTUnsyy1SN8ugStj +4NNLAVnpCtaToU1MH4V7WLk5JAQMJH40L+TGcIWk7hwbz0biC0ksIJRYuNKHpiaN7fPAcW5 gOJLGSV+bXvEBFH0hVFiwh8WEJtNQEti/4sbYM0iAikSjx+eBGtgFpjCLLF8ejNYkbCAn8Sy Mz/AtrEIqEocu/qEEcTmFXCTONW6hxFim5zEhz2P2EFsTqD41IYmFohlrhJPH29iBRkqITCT Q2LLi+PsEIMEJL5NPgRUxAGUkJXYdADqG0mJgytusExgFF7AyLCKUTS1ILmgOCm9yFCvODG3 uDQvXS85P3cTIzAiT/971ruD8fYB60OMAhyMSjy8DRyfw4RYE8uKK3MPMZoCbZjILCWanA+M +7ySeENjMyMLUxNTYyNzSzMlcV5FqZ/BQgLpiSWp2ampBalF8UWlOanFhxiZODilGhjXN6yI 8aps5D1448mG5KJIE/6eBRPkBOUW6nxZwRlSVf98ivJRxc0+PMlFciy64tNmvjcSkWcRUVVK v7bB90Sx1mH+VrU3HhP8Fi+VXKZS098Zfeioq1VS/ve1Rn3HHKOXvnlzUeGlYLBWmYfktYh3 D9epLv38vcZI5YbW+f8bThsuYr7YxaDEUpyRaKjFXFScCAD7SCD1wwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHIsWRmVeSWpSXmKPExsVy+t9jAV27nM9hBh37TC2uf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtsenyN1eLyrjlsFp97jzBazDi/j8li3cZb7Ba3 L/NaLL1+kcniduMKNosJ09eyWJw5fYnVonXvEXaLttUfWB2EPdbMW8Po0dLcw+Zxua+XyWPn rLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQDuqAZGm4zUxJTUIoXUvOT8 lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg75QUyhJzSoFCAYnFxUr6dpgm hIa46VrANEbo+oYEwfUYGaCBhDWMGdsfbGIpOCNd0XIqrIHxq2gXIyeHhICJxJvb59ggbDGJ C/fWA9lcHEICSxklfm17xASSEBL4wigx4Q8LiM0moCWx/8UNsAYRgRSJxw9PgjUwC0xhllg+ vRmsSFjAT2LZmR/MIDaLgKrEsatPGEFsXgE3iVOtexghtslJfNjziB3E5gSKT21oYoFY5irx 9PEm1gmMvAsYGVYxSqQWJBcUJ6XnGuallusVJ+YWl+al6yXn525iBMf9M6kdjAd3uR9iFOBg VOLhvcH1OUyINbGsuDL3EKMEB7OSCO/6cKAQb0piZVVqUX58UWlOavEhRlOgwyYyS4km5wNT Ul5JvKGxiZmRpZG5oYWRsbmSOO/j/+vChATSE0tSs1NTC1KLYPqYODilGhj39jz7Y+xhqHLz jEOz9j/t5a08fds/K5Y5Tk/e8PLPt1QRnu8f7W9VJyp/udG5O33VfI7tKk+Kdy9/eiU/N3GS WGSbtwU3R0Vyw8LpddqzJi3T4/LYJlN6vO7bj6sPtvHITzYV7yl/qBxX917pQK1hllXRygOC c+4JHt8W8eSrKiejVKJYBIMSS3FGoqEWc1FxIgDijCM0EQMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160323_212608_863349_EADF5B87 X-CRM114-Status: GOOD ( 10.87 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, tjakobi@math.uni-bielefeld.de, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4x12.dtsi | 106 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 99a0f4ca3d47..e5173107ed44 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -349,6 +349,112 @@ opp-hz = /bits/ 64 <267000000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; &combiner {